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The Design Of Level Shifter Circuit For GAN Driver Ics

Posted on:2019-05-26Degree:MasterType:Thesis
Country:ChinaCandidate:J W LiuFull Text:PDF
GTID:2428330590475495Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
The enhanced Gallium Nitride power device has the advantages of fast switching speed and high breakdown voltage.It can meet the needs of high frequency and high reliability systems,and will gradually replace the power devices such as silicon based MOS and IGBT.Meanwhile,the driver ICs based on GaN power device is essential.As the most important part of the GaN driver ICs,the characteristics of high voltage level shifter circuit affect the transmission delay,static power and noise suppression of the driver ICs directly.Therefore,it is of great significance to study the delay and reliability of the level shifter circuit based on the enhanced GaN driver ICs.The characteristics of the enhanced GaN power device and the design requirements of the level shifter circuit of driver ICs are introduced in this thesis.The reliability and transmission delay characteristics of the traditional level shift circuit are deeply analyzed,it is pointed out that the reason for the larger transmission delay of the traditional level shifter circuit is that the filter circuit which is used to improve the noise suppression ability increase the transmission delay.On the basis of the above in-depth analysis,a high speed level shifter circuit based on the enhanced GaN driver ICs is designed.The current mirror is used to shift the level,which effectively reduces the transmission delay of the circuit.The circuit uses a current comparator to eliminate the dv/dt common mode noise.At last it uses the current feedback control circuit to realize the current compensation of the output signal of the comparator,and improves the capability of resistance to differential mode noise,but does not increase the transmission delay of the circuit.In this thesis,the high speed level shifter circuit was realized based on the 100 V 0.5?m BCD process,and the layout of the circuit was designed,at last the layout was taped out and tested.The test results show that,under the condition of 100 V working voltage and 1MHz signal transmission frequency,the transmission delay is 9.2ns,the resistance to dv/dt noise capacity is 85V/ns,and the static current is 24?A,which meets the design requirement.
Keywords/Search Tags:GaN, Driver ICs, Level shifter circuits, Propagation delay, Reliability
PDF Full Text Request
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