Design Of IP Core For Level Converting Circuit

Dynamic power consumption is proportional to V_DD²and static powerconsumption is proportional toVDD, lowingVDDon selected blocks helps reduce powersignificantly. However, lowering the voltage also increases the delay in the design.Recently multiple supply voltages （MSV） can be used to reduce power consumptionwithout the performance degradation. The voltage domains scheme using MSV hasbeen widely used in system-on-chip （SoC） designs to reduce the unnecessary powerdissipation in non-critical function blocks. In these SoC designs, the circuit blockswith the same voltage are clustered into single voltage domain to reduce the cost ofvoltage supply network and the power consumption. However, when the low supplyvoltage （VDDL） block drives the high supply voltage (V_DDH) block, a multi-VDDsystemhas a large static current through the weakly turned-on PMOS transistor of theV_DDHblock. To prevent this current, the level shifter which converts theVDDLsignal to theV_DDH signal is necessary. In this dissertation, we completed the design of IP core for level converting circuits for multi-VDDSoC chips. The dissertation is made up offollowing aspects:1. Any module, which needs shifting a lower supply signal to higher supplysignal with dual supply voltage level shifter, will require the lower supply voltage aswell. This leads to a very huge congestion in the supply routings. In a multi-VDDSoC, the situation becomes even worse as the number of supplies increases and endsup adding further complexity and cost to the overall system. The single supply levelshifter overcomes this problem by using only one supply at which the signal needsto be shifted.2. To reduce the overhead of the level shifter, lowVDDregions are followed bypipeline flip-flop. The flip-flops simultaneously perform latching and level shifting,so called level converting flip-flops. With process scaling, leakage current powerbecomes innegitable. We propose a low power level-converting pulsed flip-flopbased on MTCMOS.3. Scan-based design is the most popular design for testability （DFT） technique.In a scan-based DFT, state-holding flip-flops are configured into scan chains in thetest mode. Scan design chains provide a way to access the internal state of a circuit. In this part, we describe a low-power level converting scan flip-flop design.