Design And Verification Of PCS Receiving Logic For A Processor Direct Interconnection

In order to meet the increasing performance requirements of the server processor,multiple processors need to be directly interconnected to form a shared multi-path server,which realizes the sharing between the main memory and the Tertiary cache between the chips,and improves the main memory capacity and the memory bandwidth.The processor direct interconnection interface technology is a key technology for implementing direct interconnection of multiple processors.It is required to implement a high-bandwidth,low-latency bus interface that supports inter-chip storage-consistent transaction-to-chip transmission.At present,the direct interconnection technology such as QPI(Quick Path Interconnect)and HT(Hyper Transport)adopted by foreign mainstream commercial processors is difficult to obtain and use.There is an urgent need to study the direct interconnection technology suitable for multi-channel direct interconnection of domestic processors.The PCIe(Peripheral Component Interconnect Express)protocol has many advantages such as wide application,high maturity and high transmission bandwidth.It can be used as a technology choice for domestic processors to achieve direct inter-chip connection.Combining the functional requirements of direct processor connection,based on the related technology of PCIe protocol,it is of great significance to study the direct interconnection port of the processor that can be controlled independently.This paper compares and analyzes the technical characteristics of PCIe protocol and QPI,HT and other chip direct interconnection technology,and finds that if the direct interconnection port is built based on the standard PCIe protocol,there will be shortcomings such as long transmission delay and affecting the memory access performance.This paper introduces a hierarchical level of direct link protocol based on the key transmission mechanism of PCIe physical layer and supplemented by low-latency data link layer.The mature mechanism of the PCIe protocol physical layer can be used to realize the underlying high-speed data serial transmission,and the data link layer is optimized to achieve lower delay transmission,and finally realizes a low-latency direct interconnection port.Processor direct interconnection requires high transmission delay,and the delay optimization design is still required on the standard PCIe physical layer.This paper is oriented to the processor direct link protocol transmission characteristics.For the low delay optimization requirements,a receiving logic circuit of the processor direct link physical coding sublayer(PCS)is designed based on PCIe.Designed in close integration with the data link layer logic to optimize transmission delays.In this paper,a UVM-based data link layer logic correctness verification environment for direct link is designed.The environment can be targeted or randomly sent a large number of test sequences,which can randomly control the link transmission delay and build link blocking conditions,and can randomly manufacture various link instability phenomena such as link loss,error packets,and random packets..Through the above various environmental functions,the correctness of the reliable transmission,flow control and other mechanisms of the data link layer logic of the direct connection port is fully verified.The verification environment has high flexibility,high reusability,and high maintainability,which greatly improves the efficiency of verification.This paper focuses on the related work of the direct interconnection port,and describes in detail the design of the receiving part of the physical coding sub-layer of the direct interconnection port.At the same time,the idea of the verification of the direct interconnection port control layer and the verification environment of the construction are introduced.The research on the direct interconnection of domestic server processor has certain engineering realization value.