Design Of Quasi-Delay-Insensitive Asynchronous Cell Library At 40nm CMOS Technology

Asynchronous circuits are not being adopted in industry due to the lack of asyn-chronous circuit design tools,techniques,and logic cell libraries.The lack of tools,techniques,and logic cell libraries makes it challenging for designers to pursue asyn-chronous circuits in SoC design.Furthermore,implementation at deep submicron sub-stantial increase in leakage power consumption.Quasi-Delay-Insensitive based Sense Amplifier Half-Buffer logic cell library is a robust class of asynchronous circuit design approach which pose overhead of delay and power consumption at deep submicron.To contribute in reducing the gap,this work present design of efficient asynchronous Quasi-delay-insensitive logic cell library using proposed design flow suitable for deep submicron CMOS implementation with emphasis on reduction of propagation delay and power consumption.The proposed design flow size/balance transistors in the logic cell via Logical Effort technique.The flow further reduce propagation delay under power constraint via Multi-Voltage Threshold technique.Such an approach is useful in deep submicron design to achieve the most balanced configuration in a transistor network while speeding/slowing the transistor for critical and non-critical paths under power constraint.The design flow is tested by developing improved Quasi-Delay-Insensitive based Sense Amplifier Half-Buffer logic cell library on 40nm CMOS technology.The basic library cells along a Muller C element were developed and tested using 1.1 V nominal voltage.The subthreshold voltage was set to 400mV with 1GHz frequency sampling under different temperatures for validation.Cadence ICFB was used in designing the schematic,symbol,layout and test circuits.The verification was performed with Spec-tre models using Cadence Analog Design Environment.The resulting logic cell library when benchmarked with predecessor libraries show improvement in propagation delay and power consumption.