| Digital circuit design has always focused on achieving better performance. One technique used is to introduce concurrency into the design. However, with ever smaller technology nodes, clock-induced problems such as clock skew begin to play havoc. The use of clock-less, asynchronous logic design helps overcome such problems through the use of handshaking protocols in lieu of clocks to control the circuit behavior. Currently there is lack of study in energy and performance relations in delay-insensitive asynchronous circuits with concurrency. In this thesis work, an asynchronous multiplier is analyzed for energy and performance relations as concurrency is introduced into the design. Three concurrent designs having two copies, four copies, and eight copies of the asynchronous multiplier, respectively, are studied with different transistor sizes. Voltage scaling is used to adjust the level of performance to compare with the non-redundant circuit. Results show that the four-copy design provides the best performance for the same active area and the two-copy design has the least power consumption at the same performance level with supply voltage scaling. Thus there is no single design that provides the optimum results for both power and performance, but only a "right" choice of design for a particular power and performance requirement. |
