Integrated Circuit Design For High Performance Low Power Quasi-Pseudo-NMOS/DT-CPL-TG Full Adder

In the first place, the thesis analyzes several kinds of full adder cells deeply and systematically, and finds their working principles. The full adder cell circuits which are mentioned in the thesis include Basic CMOS FA (full adder), CL-CMOS FA, Pseudo-NMOS FA, CPL FA, TG FA, TF FA and CPL-TG FA. Using the truth table of a full adder I deduce all the logical equations of these full adders, and I defined the symbols for complementary pass-transistor logic circuits and tansmission-gate circuits in order to distinguish both similar cricuirts. Depending on the logical equations of the full adders it is naturally for us to obtain the circuit fomats of every full adder.As illustrated in the second chapter there would be static current in Pseudo-NMOS FA. Aiming at reducing Pseudo-NMOS FA's static current and further minimizing its static power dissipation, a new design of Quasi-Pseudo-NMOS FA is proposed in the thesis. Since the gates of PMOS transistors in Pseudo-NMOS FA are connected with gound all the time the PMOS transistors are always on. In this way static current and static power dissipation exist in Pseudo-NMOS FA. A control unit is designed in the second chapter to control PMOS transistors and determine whether the transistors are on or off. The control unit realizes its function by connecting the gates of PMOS transistor in Pseudo-NMOS FA through three minimal-sized PMOS transistors. The chance of competition between PMOS and NMOS transistors is decreased at the smame time when static current in the full adder is reduced. The new design of Quasi-Pseudo-NMOS FA not only has less power dissipation but also has less delay than Pseudo-NMOS FA. In Chapter Two the schematic and layout of Quasi-Pseudo-NMOS FA are designed and the input patterns are introduced and used to test the performance of the new design in the circuit simulation.Aiming at reducing CPL-TG FA's delay and increasing the on-state current of the transistors in CPL-TG FA, a new design of DT-CPL-TG FA is proposed in the third chapter. As the NMOS pass-transistors can only transmit poor' 1' and the PMOS pass-transistors can only transmit poor '0', the threshold voltage of transistors in the pass-transistor circuits are increased. As a result the on-state current of the transistors are decreased and the delay of the ciruits is lengthened. In order to overcome the problem DT-MOS technology is introduced in Chapter Three. The theory of DT-MOS is to make a transistor having deferent threshold voltage for on and off. In this way the on-state threshold voltage is reduced and the off-state threshold voltage does not change. The noise margin of the transistor which uses DT-MOS technology does not change but at the same time its on-state current is increased. As a result of using DT-MOS technology DT-CPL-TG FA not only has less delay but also can be used in the environment of low power. After realizing the circuit design of DT-CPL-TG FA, its schematic and layout are designed and the input patterns are used again to test the performance of the new design in the circuit simulation.Based on designin Quasi-Pseudo-NMOS FA and DT-CPL-TG FA the comparison of these two...