Research And FPGA Implementation Of NAND Flash Data Storage Technology In DAS

With the rapid development of information and electronic technology,the real-time and reliable storage technology of large-capacity data is of great importance for data acquisition system.NAND Flash has the advantages of high storage density,low energy consumption,small size,strong seismic resistance,etc.It is suitable for data acquisition systems.However,due to the structural characteristics,storage characteristics and production process of the memory itself,it has shortcomings such as bit errors,bad blocks and limited service life.So how to improve the reliability of NAND Flash storage has become a hot topic in today's research.Based on the data acquisition system developed by the research group,This paper focuses on the data storage technology of NAND Flash,including the driver,bad block,wear-leveling and ECC algorithm.According to the requirement of the project,this paper presents the design and implementation of the overall logical structure of the data acquisition system,including the sub-acquisition system and the main control system.The storage subsystem is the core of the entire design.By analyzing the structure of NAND Flash,the underlying timing driver is designed and implemented,based on this,a write bandwidth optimization method based on Multi-Plane is proposed.Aiming at the shortcomings of NAND Flash with bad block and limited service life,a dynamic block detection method and a wear-leveling strategy based on address retrieval are proposed.The ECC error correction algorithm based on BCH code is studied and verified.Based on the research of BCH coding code theory,the BCH code(8416,8192,16)which can correct 16 errors is constructed according to the requirements,the design and implementation of coder and decoder are carried out.Aiming at the low efficiency of traditional serial coder and its inapplicability to NAND Flash,this paper designs and implements an 8-bit parallel coder,and proposes a greedy strategy based parallel coder optimization algorithm,which improves the coding efficiency and reduces the resource consumption.The decoder consists of finite field multiplier module,syndrome calculation module,key equation solving module based on IBM iteration algorithm and Chien search module.In this paper,the parallel optimization of syndrome calculation module and Chien search module is carried out,which effectively improves the decoding efficiency.All sub-modules and the whole system are implemented and tested based on FPGA,and the reliability of storage module is verified and analyzed emphatically.Finally,the data acquisition system is used to sample multiple sets of AC signals,and the waveform results and indexes of the acquisition are given.The test results of the sub-module and the whole system show that the NAND Flash storage technology studied and implemented in this paper can effectively guarantee the reliability of the collected data.