Research And Implementation On High-speed Video Image Real-time Storage Technology Based On FPGA

High-speed image acquisition and real-time storage technologies are widely used in many areas such as aerospace,industrial control,and video surveillance.High-speed image technology is usually applied to observations of the microscopic world,aircraft flight records,and vehicle crash experiments.Through the observation of high-speed image sequences collected,it can be clearly seen the state which an object moves at a certain moment in high-speed motion.And which allows detailed study of high-speed moving objects.However,in some special environments,people cannot directly observe images.Therefore,high-speed images need to be stored before analysis.A set of solutions for a certain type of missile testing requirements was proposed,and implement on the development board.The system uses an FPGA(Field Programmable Gate Array)as the main control core chip,and image acquisition uses the ON Semiconductor NOIP1SN0300 A high-speed image sensor,NAND FLASH as the storage medium,and the RTL8211 E as the Gigabit Ethernet GPHY chip.This article focuses on the design of a NAND FLASH memory array controller and the design of a Gigabit Ethernet image transmission system.This subject achieves high-speed video image collection without compression and real-time storage.The designed NAND FLASH controller can reach the maximum operating frequency(synchronous 100M),which is effectively improve the storage efficiency of the chip,thus enabling small-sized storage to be realized.High-speed storage of the array.The main tasks of this paper are as follows:The first is to conduct in-depth research on the NAND FALSH memory chip,to understand its composition,operation modes,and control timing,and to propose a multi-chip chip pipeline operation mode to achieve high-speed storage.The NAND FLASH controller adopts a modular design concept,and the controller is divided into an initialization module,a page programming module,a reading module,an erasing module,a bad block management module,and a pipeline operation module.Each submodule is associated with a main state machine.At the same time,the design flow and state transition of each sub-module are introduced in detail.The operating state of the controller is controlled by an external button,and each control button is debounced.Considering that the controller must ensure high-speed storage of the NAND FLASH memory array,the controller does not include the ECC check module.At the same time,the probability of bit flipping of the NAND FLASH chip using the SLC architecture is low,and this bit flipping is Storage of multimedia data has little effect.The controller designed by this system has universality and is packaged into a general-purpose NAND FLASH controller IP core.Secondly,the system image is transmitted using Gigabit Ethernet technology,and the video data stored in the NAND FLASH memory array is transmitted to the PC via Ethernet and analyzed by the upper computer software.In this paper,the IP protocol,UDP protocol,and CRC are introduced in detail.The state machine of the UDP sending module is designed.Then the UDP sending module and the CRC check module are designed using Verilog HDL hardware description language to realize the high speed of data.transmission.Finally,the verification platform of the system was bulit,and verify the design of each module of the system,including the verification of each sub-module of the NAND FLASH controller and the verification of the Gigabit Ethernet UDP transmission module.Through testing,the final design of the NAND FLASH controller can work in the DDR mode and clock frequency of 100 MHz,which is the highest frequency supported by the chip.And the actual test NAND FLASH memory array write rate is 197.4MB/s.At the same time the video image data can be read from the NAND FLASH memory array and sent to the PC for display on the computer.This program can be further applied to other fields and has a good application prospect.