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FPGA Design And Implementation Of Digital Downconversion Model Based On SDR

Posted on:2020-01-11Degree:MasterType:Thesis
Country:ChinaCandidate:P WangFull Text:PDF
GTID:2428330575489306Subject:Computer technology
Abstract/Summary:PDF Full Text Request
In the development of information technology today,software defined radio(SDR)was born,it is a use of software to dominate the hardware circuit of wireless communication technology.Among them,the softtware provides the main communication function,while the hardware equipment only serves as the communication platform,so it does not have to be eliminated with the update of the system.However,SDR system requires extremely high signal samping rate.Limited by the current hardware level,the back-end hardware device cannot process the signal with extremely high rate.At this time,the rate of the initial signal needs to be reduced.At present,DDC has become an indispensable key technology in software radio.In this thesis,SDR is taken as the background,the key technology of digital downconversion is studied,and the DDC model based on SDR is designed by using FPGA.Firstly,the basic theory of digital signal sampling,multirate signal processing,orthogonal demodulation and digital filter is analyzed.Secondly,according to the top-down design idea,DDC model is divided into four modules:digital controlled oscillator(NCO),integrated comb filter(CIC),half-band filter(HB),and low-pass filter(FIR),and their principle,structure and implementation method are studied respectively.Among them,the performance advantages and disadvantages of the two NCO generation algorithms are compared,and the characteristics and advantages of CORDIC algorithm are emphatically introduced.In addition,for the two key modules of DDC model.the implementation algorithm of NCO is optimized and the hardware design structure of CIC is improved to improve the model performance.Finally,Quartus ? 13.0 and MATLAB were used to complete the design and modeling of the DDC model,and Modelsim and MATLAB were used to conduct joint simulation verification,and the DE2 EP2C35F672C6 chip of Altera was downloaded to complete the performance analysis of the DDC model.DDC model based on SDR and designed by FPGA is different from special chip in this thesis,which has the advantages of good reconfiguration,simple circuit structure and less occupation of resources.At the same time,it also has the characteristics of stability,practicality and flexibility,and has a good application prospect in the field of military and civilian dual-use wireless communication.
Keywords/Search Tags:SDR, DDC, FPGA, Quartus ? 13.0, Modelsim
PDF Full Text Request
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