The Design And Simulation Of Phase Locked Loop Circuit

With the rapid development and the applications incerased of microprocessor and computer technology,PLL frequency synthesizers has been widely used in various electronic devices for its low cost and any frequency can be synthesized through it. Among them, the mixed-signal phase-locked loop circuit began to appear.its phase detector is composed by digital circuits,filtering and voltage-controlled oscillator are analog circuits stilly.CP-PLL is representative of this mixed-signal phase-locked loop. it had been most widely used because its advantages,they are theoretical zero static error, high-speed, high stability,etc..The CP-PLL modeling and simulation research will help companies to shorten product Research and development cycle, reduce costs, improve product quality,and win the competition in the market.Based on the analysis of linear PLL theory, the linear PLL circuit analysis method is introduced into the analysis of the CP-PLL frequency synthesizer. A simulink behavioral model of a CP-PLL frequency synthesizer is constructed through the analysis, then verify the correctness of the model. According to this analysis method, the mathematical model of the CP-PLL frequency synthesizer is also constructed. We deduced its open-loop transfer function through the mathematical model. Proposed how to design a CP-PLL frequency synthesizer stability by feedback circuit stability analysis method. On the same premise, compared the two different methods of design a 3 order 2 type CP-PLL’s loop filterparameters. Get the parameters results which meet the circuit stability requirements through quantitative calculation. By parameters results comparison, we get a conclusion that the two design methods is negligible difference which can ignored. According to the CP-PLL frequency synthesizer principle, the circuit model based on multisim is constructed. The parameters just calculated taked into the multisim model to complete the simulation and verify its correctness.Finally, the paper discussed the digital phase-locked loop based on verilog-HDL. Give a digital PLL design method completely, and realize the design by Quartus2, simulate it by Modelsim, then analysis and explanate the simulation results.