Design And Implementation Of RS+CC Coder And Decoder Based On FPGA

Channel error correction coding and decoding technology is an important technology to ensure the reliable transmission of digital communication data.It is widely used in many fields such as satellite communication and digital television broadcasting.However,with the rapid development of coding theory and information technology,the traditional error correction coding code using a single method has gradually failed to meet the requirements of some systems.For this reason,the cascading coding method with stronger error correction capability is often used in practical applications.Guarantee the performance of the communication system.In order to quickly obtain the performance of RS+CC+ convolutional interleaved cascading coding under different SNR,this paper studies the implementation scheme combining the upper computer and the FPGA slab.This paper first introduces the performance of the compiled code under the Gaussian channel.The design of the RS decoder adopts a pipeline structure,which improves the speed of the compiled code and reduces the delay.The solution of the key equation of the decoder adopts the RIBM algorithm without reversal,which saves the hardware resource consumption.Then,the performance of the(2,1,7)convolutional coded code with different code rates in the Gaussian channel is analyzed.The convolutional coding uses decoding.In order to improve the performance and speed of decoding,a soft-decision decoding algorithm with 3-bit quantization is adopted,and the hard decision has a performance improvement of 1~3 dB.In addition,the ACSU(Plus Comparison)unit contains most of the calculation amount of the decoder,which is a key part affecting the decoding speed.The design adopts a full parallel structure to improve the decoding speed.Finally,the Xilinx series was used as the development platform,and the Vivado software was used to complete the design of the cascaded code system hardware,and the function simulation was carried out.The verification on the hardware platform shows that the decoder works stably and has good performance.The hardware simulation performance of the cascaded code is consistent with the simulation performance.In addition,all the hardware algorithm modules involved in the measured cascaded code can work under the unified 200 MHz clock.The signal-to-noise length is 10010624 bit and only needs less than 30 s to complete the singlesignal-to-noise ratio performance simulation and the required algorithm.The intermediate data is uploaded to the PC via the PCIE channel.