FPGA Design Of A Viterbi Decoder

Convolutional coding has been used in communication systems including deep space communications and wireless communications. The Viterbi algorithm, proposed in 1967 by Viterbi, is a maximum-likelihood algorithm for convolutional codes. The Viterbi decoder attempts to find the maximum-likelihood function of the decoded code word against received code word. The main content of this paper is to design a Viterbi decoder with FPGA technology. In this paper, the parallel ACS (add-compare-select) Butterfly algorithm is used to find the survivor path in encoder trellis. We also use reg_exchangc algorithm to dispose the survivor path and receive the decoded results. In addition, the behavior of a design is described in VHDL. The emulated and synthesized results of this design are received by all kinds of EDA tools. Through these results the Viterbi decoder's correctness and practicability can be validated.