The Verification Of SAS Controller Module Based On UVM

With the development of the information society and the increasing complexity of System on Chip(SoC),the verification process is becoming more and more important for the whole process of chip design,but the development of chip verification capability has not kept pace with the development of SoC,The gap between the two is growing.Seeking an efficient verification method has become a top priority in the field of chip design,and the emergence of Universal Verification Methodology(UVM)verification methodology has solved the problem of inefficient chip verification in the field of chip design.UVM combines the advantages of Open Verification Methodology(OVM)and Verification Methodology Manual(VMM)to overcome the shortcomings of both.It is a very efficient verification environment development library,engineers can leverage their reusable components to build a functional verification environment with standardized hierarchies and interfaces.It can be said that UVM represents the development direction of the verification methodology.The Serial Attached SCSI(SAS)interface is the latest generation of enterprise-class storage interface technology.It is widely favored by enterprises because of its high transmission speed,good scalability,and compatibility with SATA(Serial ATA)interfaces.This paper focuses on the use of UVM verification methodology to simulate and verify the SAS controller module to ensure that the SAS controller module conforms to the SAS protocol specification.This paper first introduces the development status of verification methodology,and points out the advantages of UVM verification methodology compared to other verification methods.Secondly,the basic theory of chip verification and the methodology of UVM verification are briefly introduced,focusing on the components and their functional characteristics in the tree architecture of UVM.Then,the characteristics of each layer in SAS protocol are analyzed in detail,and the UVM scheme for verifying the SAS controller is proposed through analysis,and the components of the UVM verification platform are implemented by using System Verilog language.Completed the construction of the UVM verification platform of the SAS controller module.In addition,the written test cases are simulated and validated through the UVM verification platform.Firstly,smoke test is carried out on the test cases,and the registers and interfaces in Design Under Test(DUT)are basically verified.Then,the transmission and reception of frames and the reading and writing function of Advanced High Performance Bus(AHB)bus are emphatically tested to ensure that the design of SAS controller conforms to the standards of enterprises and the specifications of SAS protocol.In addition,the biggest advantage of this verification platform is high reusability and portability.It can be reused on a variety of solid-state memory chips,which fully reflects the advantages of UVM verification methodology.