Research And Design Of ADC For Wireless Charging

With the continuous development of electronic information industry in recent years,various portable electronic devices can be seen everywhere.As the functions become more and more abundant,the power consumption of these devices also increases.At present,the mainstream charging mode is the traditional cable charger.This method is simple and low in price,but it can't cover up many of its shortcomings,such as easy to be damaged and low safety in some environment.Wireless charging can avoid these problems.The goal of this paper is to design the ADC in the receiving terminal of the wireless charging chip.In order to ensure the normal operation of the chip,it needs to monitor the voltage,current and temperature of the internal DC-DC module in real time.Considering the anti-interference,easy to transform,storage and other factors,the receiving terminal uses digital coding to communicate with the transmitting terminal,therefore an analog to digital converter(ADC)is needed to realize the conversion from analog signals to digital signals.Based on the requirements of ADC performance in the chip,this paper mainly designs a 10bit 200kS/s SAR ADC from the aspects of precision,power and area.In this paper,the theoretical basis and basic principle of SAR ADC are introduced firstly,several common SAR ADC structures are analyzed and discussed.After comparison,this paper chooses the full differential charge redistribution SAR ADC.Then the common structure of each module of the structure of ADC is analyzed.Based on the design requirements of high precision,low power and small area,each module is designed and simulated in detail.The single-ended-to-differential circuit uses a switched capacitor circuit to preprocess the input signal.In order to keep good linearity,a binary weighted capacitor array is chosen for DAC in this paper.And it reduces the area and power consumption effectively by the monotonic switching time series and the series of unit capacitance.For the comparator,considering the problem of accuracy,the multistage cascaded open loop amplifier is used.Then,through the analysis of various non-ideal effects in the circuit,the improvement method is put forward,and the circuit structure is further optimized.Finally,based on the 0.35umBCD technology,the whole ADC layout design is completed.The simulation analysis of ADC is carried out.The static performance is simulated by a full range of oblique waves,circuit simulation results of INL and DNL are as follows:INL=0.321/-0.212LSB,DNL=0.260/-0.244LSB.Then input a sine wave of 19.95k Hz to simulate ADC's dynamic performance,it is known that SNDR is 59.979dB,SFDR is74.115dB and ENOB is 9.671bit.The simulation results show that the average power consumption of ADC is about 733.92uW under the 3.3V supply voltage,which reaches the design requirements.Finally,the layout of ADC is designed,and the layout area is0.167253mm~2.