Architecture and design of a simultaneously bidirectional single-ended high-speed chip-to-chip interface

Advances in integrated circuit technologies permit faster clocking speed and increased logic density in chips. However, advances in chip packaging technologies have not kept pace; hence the number of input/output pins and input/output bandwidth per chip has increased less rapidly. The resulting disparity creates the need for more bandwidth per pin. Single-ended signalling and simultaneous bidirectional signalling methods may each increase the bandwidth per pin by a factor of two. However, using these signalling methods poses challenges in compensating for additional noise sources and reduced noise rejection ratios.; This dissertation presents the architecture, circuit techniques, and test results for a single-ended simultaneously bidirectional interface capable of a total throughput of 8 Gigabits per second per pin. The interface addresses the noise reduction challenges by utilizing a pseudo differential reference with noise immunity approaching that of a fully differential reference. Furthermore, noise generation is reduced by on-chip termination, and low-skew near-end outgoing signal echo cancellation.; The pseudo-differential reference accurately tracks low frequency common-mode and differential-mode noise on the supplies of both chips by a novel method of comparing the data signal with a set of three partial reference signals that constitute a pseudo-differential reference. Only one of the partial references is shared between the chips. Prior methods have shared two references, which offers less accurate noise tracking. This new method achieves higher accuracy using one versus two pins.; The system cancels high frequency noise on the chip supplies by a novel noise transfer matching technique. This technique compensates for inherent physical differences between the pseudo-differential reference and the plurality of data signals that share the reference. The method also permits either current-mode or voltage-mode signalling, and for near-end outgoing signal cancellation of a predistorted signal, allowing transmitter-based compensation of inter-symbol interference.; The receiver includes a new multi-input capacitive-averaging sense amplifier that tracks and amplifies the linear analog function of four signals needed to implement the pseudo-differential reference method. The transmitter includes a novel source-terminated, voltage-mode output driver that drives a predistorted output signal while maintaining a constant output impedance. Both the receiver and transmitter are multiplexed to allow for operation at high speeds.; A test chip in a 0.35 micron digital CMOS technology uses these techniques for an eight bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gigabits per second per pin.