Research On Using Active Logic Reduction Technology For Timingbudget

With the increasing integration of digital integrated circuits,process nodes become smaller,the scale of chip design is getting huge.It is an important and complex task to ensure the timing convergence of large-scale chips after the physical design is completed.For this reason,in the initial stage of the back-end hierarchical physical design,it is necessary to generate a plurality of different floorplan and timingbudget results to guide the next design.The timing budget of large-scale chips requires EDA tools to perform long time calculations and occupy a lot of computer resources,extending the design cycle of the entire chip.Therefore,a fast,accurate and significant reduction in resources timingbudget method has become the key to large-scale hierarchical physical design.This topic is based on active logic reduction technology to simplify the circuit logic netlist of each partition module in hierarchical physical design,construct a simplified circuit logic netlist like interface logic model,and carry out timingbudget based on this simplified logic netlist.A new timingbudget method is obtained which reduces the computation time and significantly reduces the computational resources compared with the original method.Using Cadence's digital back-end design software innovus to accomplish a back-end hierarchical physical design of a DTMF signal transceiver chip using TSMC 65-nm nodes process.The new timingbudget method is used to perform a rapid timingbudget result for this design,and the design will be partitioned according to the results of the timingbudget.After completing the placement,power planning,clock tree synthesis,and global routing,each partition module will be assembled at the top level.Through timing verification,logic equivalence verification,and physical design rule verification,which will illustrate this new timingbudget method not only can reduce the computation time of the EDA tools and the memory consumption of the computer,but also the result of the budget is sufficiently accurate that the result will reach to design timing requirments.This proves the reliability of this new timing budget method.The new timingbudget method proposed in this paper is based on active logic reduction technology.It can significantly reduce the time and computer memory consumption during timingbudget compared with the traditional method.The greater the size of the redundant logicinside the design module,the more obvious the effect of this kind of timingbudget method on the calculation time and the amount of memory used.Comparing with original method,in a module which contain 7533818 instances.the calculation time is reduced by 30.80%,the memory occupied by the computer is reduced by 35.16%.This greatly shorten the timing of the timingbudget and the physical design cycle of the entire chip.