The Design Of Memory Controller Based On FPGA

With the arrival of the era of big data,the development and popularization of information technology lead to an explosive growth of data,this all require higher performance of storage systems.Due to complicated operation,inconvenient upgrade,and slow storage,the traditional architecture is unable to meet the storage requirements of massive data,which designs storage system only by FPGA.Therefore,it is necessary to design a storage controller that can achieve high-speed storage and easy data management.Under such circumstances,this thesis designs a new CPU+FPGA architecture memory controller based on the actual project requirements.Through the analysis of the project's functional requirements and technical indicators,this article forms a storage array with multiple SATA interface SSD in a RAID0 manner to expand the storage capacity of the storage system.The high-performance CPU and FPGA are the main controller of the storage system.The CPU,RAID controller and FPGA are connected through the PCIe bridge.The PCIe3.0 protocol is used to increase the data storage speed.The DDR3 SDRAM memory is used as the system cache.Through the memory mapping technology,the space of the DDR3 SDRAM on the FPGA is mapped to the CPU.Thereby,both the CPU and the RAID controller can interview the DDR3 SDRAM memory space on the FPGA,so that the data can be directly stored in the SSD without going through the CPU.Combining the above design ideas,this thesis mainly completes the following works: First,it introduces the background and significance of this study,then introduces the research status and development trend of storage controllers.It also studied the various architectures of existing storage systems.Second,based on the project's requirements of the storage controller,the overall programme with detailed descriptions is proposed.In combination with the transmission characteristics of storage arrays,the DMA transfer mode is designed to greatly increase the data storage speed.Finally,according to the specific requirements of the project,Xilinx Virtex-7 series FPGA and Vivado development tools are selected as the development platform.The Gigabit Ethernet,GTX,DDR3 memory controller,PCIe port is designed in a modular way,and the all interfaces have been debugged.Meanwhile the basic self-test,record,playback,upload,download and other functions were initially implemented on the FPGA.This system is tested by Vivado's in system debug debugging tool.The final test results show that the scheme using FPGA and CPU together to design the storage controller is clear and the design is reasonable,which can meet the requirements of high data throughput rate and high data processing speed.After repeated tests,the system is stable and has excellent performance,which meets the requirements of the project.