Logical Design And Implementation Of Memory Trace Collection Tool

In recent years, the improvements of memory performance have become the bottleneck of the entire computer system. It is very important for the analysis of the behavior of big data applications to get large amounts of detailed memory trace from the whole system in the study of memory architecture quickly. Besides, with the data rate on the memory bus rising, some of the existing memory trace collection tools has been unable to collect the memory trace of high memory access bandwidth applications accurately.Therefore, in this thesis, the author redesigned and optimized the FPGA logic of the existing HMTT v3 memory trace collection platform to meet the needs of current memory trace collection. The primary works in this thesis are presented as follows:(1) This thesis improved the DDR3 data rate which the HMTT v3 memory trace coll ection platform supported from DDR3-800 to DDR3-1600;(2) This thesis makes it possible for HMTT v3 memory trace collection platform to process 4-way DDR3 command, address and control signal in parallel, and output the corresponding memory trace information;(3) By using two kinds of different memory trace packet format, this thesis can easily compress the memory trace packets while keeping the entire memory trace information including the total memory time interval complete;(4) To meet the requirements of the transmission and storage of memory trace packets, the thesis studied and implemented the function of accurately transmitting memory trace information to the receiver without any packet loss via PCIe channel;(5) This thesis implemented the expansion of HMTT v3 memory trace collection platform to support multi-memory environment, and implemented the function of collecting trace from two memory sockets in the same channel at the same time.The work done by this thesis made it success to collect memory trace in the speed of DDR3-1600 on HMTT v3 memory trace collection platform. The memory trace collected can be accurately transmitted to the receiver for storage. At present, the work done by this thesis has been used to collect the memory trace of multiple big data applications, providing strong support for the analysis of the big data applications' behavior. The results of that analysis have been used to design and optimize some new memory architectures.