Hardware Design And Implementation Of Near-field Antenna Test Receiver

With the rapid development of radar technology,the scale of modern radar equipment is growing,its function is more and more complex.The antenna measurement technology is becoming more and more difficult because of thousands of T / R components in radar equipment.In particular,the Phased Array Radar used in modern war requires the test results of the antenna to be rapid and accurate.At the same time,it also requires the test equipment become flexible.Therefore,this thesis designs one kind of near-field antenna test receiver,which is based on the reference channel and measurement channel data acquisition mode.The parameters such as the output frequency and power of the local oscillator and the excitation source are controlled by the trigger signal of the positioning machine.These signals output to the measured antenna,radiation to the test receiving antenna,measure the amplitude and phase information of the signal by high efficient multi-channel data acquisition.The test receiver is flexible,fast and accurate,which can meet the requirements of modern near field antenna test receiver.The near field antenna test receiver adopts the combination structure of the acquisition module based on the FMC bus and the digital processing carrier plate.The FMC acquisition module adopts the modular design idea to complete the data acquisition function of the antenna test.In this thesis,two kinds of FMC acquisition modules are designed to complete the 2/4 channel acquisition function,which increases the flexibility and versatility of the system.Two channel FMC data acquisition module mainly completes the large dynamic range,high precision signal acquisition function,the four channel FMC data acquisition module can complete the four channel,the highest 1.5GSPS data acquisition function.By designing different data acquisition modules,the sampling capability of the system is expanded.The data processing board is a digital processing circuit based on FPGA.According to the requirement of the test,the high speed receiving and down conversion processing functions are designed on the carrier board;In order to meet the requirements of large capacity data storage in the test receiver,the thesis designs a data buffer circuit of onboard DDR3 memory;In order to facilitate the user to observe and capture the useful signal,designed three trigger mode,the trigger signal can be cached to the DDR3 memory and then sent to the host computer;The function of fault detection and display is designed,which increases the function of checking and protecting the system;In the data processing carrier board and the host computer connection program,introducing the PCIE interface logic design and implementation method.In this thesis,the correctness of the design program is verified by the test of the FMC data acquisition module and the whole performance of the antenna test receiver.The amplitude ratio error of the antenna signal measured by the near field antenna test receiver is in the range of 0.2dB,and the phase difference error is in 2 degrees,which meets the expected design requirements.