High Speed Mass Image Data Storage Reliability Research

With the development of modern science and technology, the accuracy of the instruments and data acquisition devices is getting higher and higher, which causes a higher demand for mass data storage system. Data security must be ensured when the dates are stored in high-speed and massive storage system, or storage system will lose its original role. In this paper, a high-speed mass storage system was designed based on NAND Flash and the reliability of data problem was solved.The current development of high-speed mass storage system is analyzed and the significance of the topic in the mass storage system of high speed camera is also given. The hardware platform in this topic is a storage system based on NAND Flash. The experimental board uses two NAND Flash chips to do research, but the final design of the hardware system is composed of144NAND Flash. This design using FPGA control multiple NAND Flash chips to work in parallel pipelining can greatly improve the reading and writing speed of storage system, so high-speed mass data storage can be achieved.The problem of bad block management exists because of using NAND Flash for storage media. Bad block management includes bad block identifying, bad block storing, bad block skipping and bad block replacing. In bad block management method, the detected effectively block address is stored in the built register, which can save FPGA internal resources and accelerate the speed of operation of the NAND Flash. When used block is operated again, the concept of exchange block is introduced, which can reduce the overall block erased times, making the service life of the NAND Flash chips longer. ECC checking method and wear-leveling algorithm are used when NAND Flash chip is operated, which can ensure the reliability of the storage system and the maximum service life.The basic idea of this design is using the parallel pipelining operation of multiple NAND Flash chips to achieve high-speed and massive storage system, while using the bad block management algorithms to ensure the reliability of data storage. Finally, using the simulation of logical code and the output results of experimental board verify the result. Simulation and experimental results prove the feasibility of the design and the reliability of bad block management algorithms.