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The Design And Realization Of A High Speed And Large Capacity NAND FLASH Storage System

Posted on:2016-04-04Degree:MasterType:Thesis
Country:ChinaCandidate:Q LiFull Text:PDF
GTID:2298330452464938Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development ofmodern radar and other electronic technologies, therequirement of the signal processing system for high-speed and real-time data storage ismore and more strong. In order to meet its growing performance of high bandwidth andlarge capacitystorageneeds, this paper designs a high-speed and large-capacity NANDFLASH storage system with FPGA as the master control of it.Firstly, this paper made an intensive study of the storage technologies and a variety ofhigh-speed interconnection technologies, and then proposed a storage structure ofhigh-speed and large-capacity NAND FLASH storage system based on FPGA. In view ofthe core NAND FLASH storage array of this structure, it used multi-group andmulti-channel NAND FLASH and made full use of the sets of instructions to achieve aparallel pipeline control method, which greatly improved the bandwidth and capacityperformance of the storage system. This paper also focused on the design of manyhigh-speed data flow path, it adopted SRIO, PCIE and1000M Ethernet to realize thecontrol of the data transmission path, command transmissionpath as well as the monitoringtransmissionpath.Secondly, this paper also aimed at the study of bad block management, ECC algorithm,wear leveling and the file system. These techniques not only avoided the influence of thebad block to the properties of the storage system, but also ensured the reliability of thestorage system, left the system a long service life.Finally, this paper used the leading NAND FLASH and its chip technologies in theindustry and applied the NAND FLASH storage structure which was controlled by a FPGAto finish the design of astorage board. The board’s capacity is1.5TB, and its writtingbandwidthis950MBps and reading bandwidth is more than1.0GBps. With the detailedanalyses of the board’s structure and the software design of the FPGA, as well as theimplementation of many high-speed interconnection interfaces, the paper finished thecapacity and bandwidth performance test of the board. After the calculation of itsperformance indicators, it can all achieve90%of its theoretical value. According to therequirements of the actual project, this paper designed a large-scale and high-speedcollection and storage system, which finished the high-speed storage and the real-time controlling of the data under the four types of the storage system’s modes. It greatly provedthe feasibility of the design of the high-speed and large-capacity NAND FLASH storagestructure in the system platform.
Keywords/Search Tags:FPGA, NAND FLASH, Bad block management, ECC, File system, High-speed Interconnection technologies
PDF Full Text Request
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