Research On Physical Design Of DMA Module Based On 28nm Process And Global Bus Interconnection Technology

With the progress of IC technology and the decrease of transistor size,it brings severe challenges to the physical design.In the first place,smaller feature sizes allow engineers to integrate more transistors per unit area,while smaller transistors have greater leakage power.This makes the power problem more important.At the same time,the progress of technology has changed the structure of interconnected metal,making the interconnection delay an important factor affecting timing convergence.Especially for the long distance bus interconnection in top level,it is difficult to repair in the later stage when timing violation occurs.This paper,based on the actual project,starts with the physical design of the DMA module,studied the power and interconnection problems in order to reduce the power consumption and interconnect delay in 28nm process.First,the physical design of the DMA module was completed,including the specific flow of placement and routing and static timing analysis,and the power optimization and timing repair process of ICE.Then the problems and solutions of DRC in this process are studied and finally tape-out was successful.On this basis,the composition and source of power consumption are analyzed.By adjusting the area of the module many times,observing the timing and power consumption of the modules after the automatic placement and routing under different area conditions.And the most suitable area of the DMA module is found.After that,it was the optimization of the time of the clock repeaters.The test found that automatic optimization of the tool will greatly increase the latency and skew of the clock tree.In this paper,the substitution scheme that keeps the clock latency basically consistent in this process was found by using the substitution function in PrimeTime,and the time of clock repeaters of the DMA module is optimized by using the script.After the adjustment and test,the most suitable area for this DMA module is 750X850um~2;after the substitution of the clock repeaters,about 80%clock repeaters'time is reduced and the power consumption of the clock inverter is reduced by 22%.Finally,compared with the module that optimized by the standard process,the total power consumption of modules under ML and TC corner is reduced by 8.6%and 10.1%,separately.For interconnection problem,the source and optimization method of interconnect delay and crosstalk delay are analyzed.The position of repeater is optimized by the method of interleaving,and the interconnect delay of the global bus is optimized by the way of pre-layout of script.And by testing different times and different insertion distance of repeater,the insertion scheme that can minimize the interconnect delay in this process was found.In this paper,the pre-layout script is completed and the interconnect between the Core7 and L3in the multi core DSP chip is optimized using 13-time inverter inserting at 400um based on test results of the insertion scheme.Compared to the result that optimized by the APR tool,it ultimately reduced the interconnect delay by 66%and the crosstalk delay by 70%.