Research And Applications Of Incremental Interconnect Delay Optimization Methods

In deep submicron technology,interconnect delay has become a major component of delay inthe chip design.Therefore,how to optimize the interconnecting wire’s delay has become anproblem which must be considered and resolved in integrated circuit design.Incremental interconnect delay optimization method is given for different interconnect.It isbased on EDA tools optimized on the basis of further optimization of interconnect delay,focusedon solving the critical path in the wire detouring problem and long wire problem.Two incrementalinterconnecting wire delay optimizing methods are given based on theoretical analysis andexperimental verification,namly CBTS(cut-off bends to straight) and Load Spliting.The advantageof CBTS is the targeted re-optimization after EDA tool optimization.CBTS is used to solve thewire detouring problem caused by the delay in the design The key is the absolute difference ofmore violation of the path of displacement and distance.Based on this basis,construct CBTSoptimal conditions and propose the implementation algorithm;load split is primarily used to solvethe problem of long wire cause of the delay,the load spliting by a large number of experimentalconstruct load split the optimization of conditions,given the algorithm.Load spliting process intothe buffer and adjust drive technology a lot of experiments and analysis.Finally,two incremental interconnecting wire’s delay optimization methods which are CBTSand load spliting are verified in the experiments by different design modules.The result is that CBTS has a performance increase about2.3%to9.27%based on EDAoptimization,and violation of the path reduced by0.42%to4.7%;load splitting has a performanceincrease about1%to7%based on EDA optimization,in violation of the path a decrease of1.2%to7.14%;Accordingly,the correctness,practicality and superiority of the two optimization methodshas been verified in integrated circuit design.