Analysis Of Chip Delay And Temperature Characteristics Considering Thermal-Electric Coupling Effects

With the rapid scaling down of the CMOS device technology, the thermal related issues are becoming one of the most challenging problems in deep submicron(DSM) IC design, and interconnect delay evaluation is also a crucial concern in DSM IC designs. One hand, inductance is becoming more important with faster on-chip rise times and longer wire lengths, and must be included in the delay model. In addition, temperature affects delay, and need taken into consideration in the delay model as well. On the other hand, decreasing feature size, higher integration density and rising power consumption lead to higher temperature and temperature gradients, further influence on delay, power consumption and reliability. For the interconnect delay dependence on temperature distribution, two delay models suitable for different conditions are proposed in this paper. One model has analytical expression which takes inductance and thermal effect into account, the other can de used for delay estimation with space-time temperature distribution, and also has analytical expression. At the same time, two power optimized methods by repeater insertion are presented in this paper. They are based on the thermal-electric coupling effects among delay, power and temperature, and makes power consumption reduced by allowing a small delay penalty. The first method gains the optimized results by using Matlab software. The second method is based on the fact that convergent results reflecting the feedback between power and temperature and found by using the available power model and HotSpot software, and addresses full chip temperature distribution that is achieved by HotSpot software and takes delay, power, temperature and temperature gradients into consideration. Both of the above methods are design methods considering temperature, and pay attention to the temperature impacts on carrier mobility, the interconnect resistance and power during each step. Delay models and power optimized methods are also simulated in this paper. Results show that the two proposed delay models have more accuracy and are very high in simulation efficiency, and also show that the chip temperature and power optimized by the tow presented methods are decreased. In addition, the first power optimized method points out that those available methods without considering inductance lead to underestimate optimal temperature and power, and the second can make temperature gradients optimized.