The Research Of Repeater Insertion Methods Under 40nm Technology

After integrated circuit technology enter nanometer process, the delay of interconnect has become a dominant factor affecting the system delay. In order to guarantee the chip to achieve the goal of the timing convergence, the optimization of interconnect delay is particularly important. The technology of repeater insertion is one of the most common and effective method to reduce the interconnect delay. Based on the actual project, this paper has made researches for inserting methods of repeaters under the 40 nanometer technology, aiming at the interconnection problem in the back-end design of the high-performance microprocessor chip.Firstly, inserting methods of repeaters for optimizing point-to-point interconnect delay. This paper performs experiments for inserting methods of repeaters, using a large number of repeaters with different wire length and types. Experiment results have shown that as the drive multiple increases, the delay of the same length interconnect decreases gradually, but the area and power consumption increase. Synthetically considering the consumption such as delay, power, area and so on, the better interconnect length is 200?m~300?m and the better type of repeater is 12-time inverter.Secondly, inserting methods of repeaters for optimizing global interconnect bus delay. The paper optimizes and assesses the inserting methods of repeaters, aiming at the problems of delay, crosstalk and congestion resulted from so much global interconnect bus existing in the limited area between the modules. We optimize the position of the repeater by the method of interleaving and also optimize the parallel bus by the special routing rules. The analysis results of experiments shows that this method can reduce the local congestion and crosstalk effectively and decreases the delay of global interconnect. This method reduce total delay and crosstalk of interconnect by 25.4% and 21.8% separately.Thirdly, inserting methods of repeaters for optimizing multiple fan-out interconnect net delay. As there exist some multiple fan-out interconnect net in the design, using EDA automatic tool optimization maybe makes the number of repeaters too much, resulting in high density of local cell and congestion. This paper proposes a method for optimization of repeater insertion which considers the lengt h and congestion. This method can decrease the number of repeaters, ease the congestion problem and it also can optimize the interconnect delay. The analysis results of experiments shows that comparing with EDA automatic tool optimization, this method can reduce the inserting series of repeaters by 8, decrease the total delay of path by 237 ps, and reduce the density of cell by 16.7%.