Study Of Bias Temperature Instability Based On 65nm Commercial CMOS Process

As the process nodes of integrated circuits are continually updated and upgraded,the feature size of the device is reduced to an ultra-deep sub-micron stage,which makes device reliability problems increasingly serious.Bias temperature instability effect?BTI?has received more and more attention as a direction of integrated circuit reliability research.It usually occurs under the condition of applying high temperature and gate voltage bias to the MOS device,which will cause the absolute value of the device threshold voltage V_th to increase,the drain current I_d and the transconductance g_m to decrease,and the off-state current I_off to increase,thereby finally This may cause the MOSFET device to malfunction.This article has done the following research on devices in the 65nm CMOS process.Test structure design and test system construction.The test structure of the BTI effect was established according to the JEDEC standard,and the layout of the test structure was completed using the integrated circuit EDA tool Virtuoso.Finally,the layout was delivered to the process manufacturer,using the semiconductor parameter analyzer Key-sight B1500A,Cascade probe station and The ESPEC-ETC200L incubator was built with a test system to complete the accelerated test.BTI effect study.Firstly,the NBTI effect of the 65nm PMOS device was studied.The output characteristics and the transfer characteristic curve of the PMOS device before and after the stress were tested.It was found that the drain current showed a certain degree of degradation after the device was degraded.At the same time,the change of electrical parameters of PMOS devices after stress is tested.The effects of four factors,such as gate stress voltage,stress temperature and device size?gate width and gate length?on the negative bias temperature instability,are discussed.The degradation trend and regularity of PMOS devices under different conditions are summarized.Then the PBTI effect of the 65nm PMOS device was studied.The output characteristics and the transfer characteristic curve of the NMOS device before and after the stress were tested.It was found that although the threshold voltage of the device drifted,the offset was very small,indicating that the PBTI effect of the 65nm device is not obvious.Life evaluation.The threshold voltage drift amount?V_th can be used to characterize the NBTI lifetime of the PMOS device.Studies have shown that?V_th is affected by the gate stress voltage V_gs,the stress temperature T,and the device size?W,L?.The relationship between gate stress voltage,temperature stress,gate width and gate length and threshold voltage drift?V_th is discussed separately.According to the experimental data,the experimental expression of?V_th is obtained.Finally,the NBTI lifetime of PMOS device is derived.The experimental results provide a reference and life prediction basis for the application of the 65nm commercial CMOS process in the field of high reliability and degradation modeling.