Design Of 22Gb/s VCSEL Driver Circuit In 65nm CMOS Process

Since venturing into the 21st century, the explosive growth of information sets higher requirements for the transmission speed of communication system. In short distance interconnection, there are two kinds of technique, electrical interconnection and optical interconnection respectively. Compared with the traditional electrical interconnection, the new emerging optical interconnection technology, taking light wave as the carrier of information, has a significant advantage in high-speed interconnect. The development and maturation of Vertical Cavity Surface Emitting Laser (VCSEL), has further removed the obstacles on the price for optical interconnection replacing electrical interconnection.The VCSEL drive circuit researched and designed in this paper, lying at the end of optical interconnect communication system transmitter, is the core module of the transmitter. Based on 65nm GP CMOS process of TSMC, the circuit adopts current driving and uses pre-emphasis waveform compensation technique to improve eye diagram quality. And the whole circuit is composed of 50Ω input stage, limiting amplifier, voltage controlled delay line and a drive stage. The input stage completes the impedance matching and DC level loading; the limiting amplifier amplifies and shapes an input signal as the main driving signal; the voltage controlled delay line produces a delay signal for the main drive signal; the drive stage ultimately realizes pre-emphasis waveform compensation and outputs the compensated current. In order to achieve the modulation and bias current digital control with high precision, the drive stage is designed to 5 copies, with the same structure and size ratio 1:2:4:8:16, each copy controlled by the corresponding digital-bit. Current mode logic structure is adopted in the high speed signal path to improve the working speed.The final circuit chip area is 1045μm×410μm. The pre-simulation results show that the modulation and bias current digital control precision achieve a differential nonlinearity error less than 1LSB, while the integral nonlinearity error is less than 2.5LSB, in all process comers and 0℃～85℃. The post-simulation results show that the circuit can obtain a good eye diagram at 22Gb/s in all process corners and 0℃～85℃, still it can work at 25Gb/s, with total power consumption less than 60mW in the standard output current condition.