Simulation And Testing Of NBTI Effect Of 65nmMOSFET

With the CMOS technology progress and device's feature size scaling down,Negative Bias Temperature Instability?NBTI?effect has become one of the key factors that affect the reliability of PMOS devices.NBTI effect causes the degradation of PMOS devices performance which reduced the lifetime of PMOS devices and CMOS integrated circuits.In this paper,the influence of the NBTI effect on the PMOS lifetime has been studied under the SMIC's standard 65nm process.First,this paper introduced the widely accepted R-D Model in NBTI effect and the related derivation of the model.Besides,the simulation of the degradation characteristics in PMOS were studied with the simulation tool of the Sentaurus TCAD.The effects of temperature,gate voltage and other factors on the device degradation were studied in detail,it is found that the greater temperature and the higher gate voltage,the more serious the degradation of the device characteristics.In addition,the smaller the thickness of the gate dieletric layer,the faster the generation of the Si/SiO₂ interface defects and the more serious the degradation.Second,the effects of the fluctuation in STI and Halo injection process on the NBTI lifetime of the device were also analyzed by simulation.With the uniaxial compressive stress generated by the STI increased,the NBTI effect reduces to a certain extent,and the lifetime of the device is increased.When the channel doping concentration increased by the fluctuations of Halo injection process,the electric field in the gate oxide increases,aggravating the NBTI effect and reducing the lifetime of PMOS devices.And the fluctuations of Halo injection process influence the NBTI effect much more significantly than the STI process.In addition,according to the design rules of SMIC standard 65nm process,the test structures of PMOS device with different width ratio W/L,gate length L and antenna structure were designed,the experimental schemes of NBTI stress test were planed,and the relevant stress parameters are determined.Finally,the NBTI experiments were carried out based on the test structure,and analyzed the difference of PMOS characteristics before and after NBTI stress.It is found that the threshold voltage degenerates most seriously than the others,so this paper taken the shift of threshold voltage as the evaluation criteria of PMOS lifetime.The effects of stress time,gate voltage,temperature and device dimension on the lifetime of the device were studied,and the relevant stress parameters are extracted and,then a formula was presented to estimate the device lifetime under the SMIC's standard 65nm process.