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Keyword [65nm process]
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1. Design Of Standard I/O Cell Library In 65nm Process
2. Design Of A 256Bit EFuse In 65nm Process
3. Design Of High Speed And Soft Error Tolerant Arithmetic Units In 65nm Process
4. The Design And Implementation Of High Speed SRAM In L1 Cache Tag Under 65nm Process
5. Design Of The Charge-Pump PLL Based On The 65nm Process
6. The Full Custom Design Of High Speed Low Power SRAM Under 65nm Process
7. Research And Design Of A Novel Testing System For Single-Event Multiple Transient In 65nm Process
8. Research Of A Mm-wave Oscillator With Frequency Selective Negative Resistance Tank Based On CMOS 65nm Process
9. 6.25Gbps SerDes Transmitter Design Based On 65nm Process
10. Design Of Non-volatile SRAM Cell Based On RRAM In 65nm Process
11. Simulation And Testing For HCI Effects In 65nm NMOSFET
12. The Study Of Copper Interconnect Reliability Based 65nm Process
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