Pre-emphasis And Balanced High-speed Cml Interface Circuit Design

As the increase of the data rates of communication systems, the differential serialsignaling has been used extensively in high-speed data transmission systems. However,the effect of bandwidth limitations in baseband channel deteriorates the signal integrityseverely, which put an obstacle to increasing the data rates up to muti-Gbps. In order totransmit data in a higher data rate, the high speed interface circuit with equalization hasbecome an important research direction.This dissertation develops a high speed CML serial interface circuit andimplements the circuit in130nm CMOS to enable10Gbps serial baseband datatransmission over backplane. The channel loss at the Nyquist frequency is18.7dB. Acontinuous-time5-tap FIR filter is used as a transmitter equalizer, while a2-tap DFE isused at the receiver side. An novel Loss of Signal Detect(LOS) circuit is also designedin this work. The following research topics are included in this dissertation.1) Study of the nonideal factors that affect signal integrity in baseband datatransmission systems, the necessity of equalization to compensate for channel-inducedISI is analyzed.2) Study of bandwidth extension techniques in the design of high speed analogcircuit. Inductive peaking, negative Miller capacitance and active negative feedback arestudied and demonstrated in this dissertation.3) A design procedure to systematically design a chain of tapered CML buffers, ofwhich the delay is expected minimum, is studied.4) Study of how equalizer works, a5-tap pre-emphasis circuit and2-tap decisionfeedback equalization circuit are designed to enable the transmission in channels ofwhich the signal integrity is deteriorated severely.5) Design of an novel LOS circuit which can counteract the effect of temperaturevariation on circuit.