Fpga-based Control Of High-speed Data Acquisition System Design And Realization

The data acquisition system is an indispensable and important component of the signal and information processing system, and also the core module in the Software Defined Radio system. Its application in modern Radar systems and wireless base station systems are more and more broad. In order to meet the needs of self-adaptability and flexibility of the Software Defined Radio receiver at present, and fully reflected the design ideas of the SOC system on the high performance FPGA platform, the thesis suggested a scheme of designing the high speed data acquisition system which is composed of high speed and high resolution A/D converter, high performace FPGA, PCI bus interface and DB25 parallel interface. As the control center and transmission bridge, FPGA played a very important part in this system. Utilizing FPGA not only accomplished the whole digital circuit and also highly improved the adaptability and flexibility of the system.In the sequential digital logic design, utilized abundant sequential resources in the FPGA just as PLL, Dff, FIFO and Counter, realized exactly control to the input and output clocks of the system, and can easily modify each sequential delay in the system.In the memory design, utilized the embedded RAM in the FPGA which can be easily resized to meet the needs of the system, and can easily merge or divide datas and change their transfer rate.In the transmission interfaces design, there are two kinds of transmission mode. Through logic control of the FPGA, the system can transfer datas by the parallel interface or PCI interface.In the working process control, utilized the VB program to design the control software on PC, then realized the communication between PC and FPGA. This can facilitate the control of the system on PC.In the process of debugging, utilized the SignalTapII logic analyzer to verify the datas during the whole transmission process while the system was working. This can be easier to observe numbers of pins on the FPGA than using some common test equipments.The thesis detailed analyzed the logic design of all function blocks in the FPGA and given exactly simulation results for each block. In other chapters, the thesis also detailed introduced the hardware circuit design, parallel interface design, PCI interface design, control software design, and the way of using SignalTapII embedded logic analyzer in the process of systematic debugging. It has given analysis and discussion to the systematic simulation results and test results. Besides, the thesis also enclosed the PCB diagram of the system, the logic schematic diagram of the FPGA and some relevant program lists with detailed annotation.