| In recent years,people's demand for data storage of smart mobile terminals is increasing,demand for data processing speeds and battery operation time has also been increased.LPDDR(Low Power Double Data Rate)SDRAM has been widely used in mobile devices because of its low power consumption and high storage density.So far,it has been developed to LPDDR4 and its interface transfer rate is up to 400MB/s.The continuous increase of transmission rate provides the system with faster data processing speed and wider processing width.The SOC chip communicates with the off-chip SDRAM through its internal LPDDR4 high speed I/O in real-time.The transmission interface is the communication hub between the chip and the memory.Nowadays,the integration of SOC chips and memory SDRAM through SIP packaging technology has become mainstream.The internal interface and off-chip SDRAM are connected through BGA package.This technology has achieved system-level integration and increased area utilization.At the same time,the limited exposed pins of the chip drastically increase the complexity of the test.How to ensure good connectivity between interface and memory and how to prevent the transmission interface from becoming a short board between the chip and the memory? How to ensure the interface to achieve the function? All those problems need to be solved by testing.Based on the in-depth study of the LPDDR4 SDRAM standard released by JEDEC,the key factors that must be met for the interface has been analyzed by this paper,and also the functions implemented by the LPDDR4 high-speed I/O interface has been described.Refer to the testability circuit design of the chip and the interface module,the interface's test plan including the pin circuit test,the clock frequency and the ADPLL BIST test,and also the testing requirements for the automatic eye width test are proposed and the corresponding test scheme are designed.Test cases are written according to the proposed test scheme,and a tool is used to convert test cases into test vectors,then the vectors are simulated to verify its theoretical feasibility.Because the simulation cannot reflect the signal strength and intensity,parasitic capacitance and driving ability of the device,so the test implementation on the ATE is continued.Mark the register bits that need to be captured in the test vector,run the modified test vector,and then collect the results after the completion,after that,python code is written to analysis test results,and JMP data analysis software is used to analyze the data results to verify the feasibility of the actual test plan.All of above work provide theoretical support for mass production chip testing.Finally,based on the test results and the understanding of the LPDDR4 high-speed I/O interface,a new test requirement is put forward,a theoretical test method was given,and a simple simulation was performed to verify its feasibility in MATLAB.Besides,put forward the optimization scheme for improving pin circuit fault coverage test. |
