Research For Thermal Fluctuation Source Of Ising Architecture Computing Based On CMOS Process

For the von-Neumann architecture computer,the complexity of the problem grows exponentially with the size of the problem,the time to get the global optimal solution also increases with the problem size.The Ising architecture computing system simulates the lattice spin of ferromagnetic materials,and maps the combinatorial optimization problem to the interaction coefficients between lattice spins.The spin configuration with the lowest energy of the system is the optimal solution of the combinatorial optimization problem.It can greatly reduce the solving time.Based on CMOS process to realize Ising architecture computing,the spins and interaction coefficients are stored in the SRAM cells,and the next state of the spins are determined by the logic decision circuits.But the local search of Ising architecture can make the state of the system fall into the local optimal solution and can't get out.It needs the thermal fluctuation source to make the system accept the state which increases the system's energy with a certain probability,so that it can reach the system's global optimal solution in the process of annealing.This paper has done the following main work and innovation to realize the thermal fluctuation source of Ising architecture based on CMOS process.1)we propose the SN-RRD method that randomly generates read damage by using the inherent noise of SRAM.The SN-RRD method adjusts the size ratio of the transfer transistor to the pull-down transistor in the SRAM cell,controls the amplitude of the intermediate node voltage by controlling the precharged voltage of the bit line,and makes use of the noise voltage to make the SRAM cell flip in a certain probability.So random is introduced.2)We propose the SN-TFS method to realize the thermal fluctuation source by using the SN-RRD method.8-T SRAM cells are used to store spins in the SN-TFS method.It adds two transfer transistors to the 6-T SRAM cell for the implementation of read damage so as not to affect the normal read and write operations on spins.While the global word line and independent bit lines are increased to make the read damage on the SRAM cell easier to control.3)We propose a novel interconnection structure to reduce the time for read damage.Since read damage does not require reading the detail content stored in the cell,a single read damage operation in the new interconnect structure can cause all of the spins to flip in a certain probability,which reduces the damage time and increases the proportion of effective computing time comparing to the scheme realizing read damage by row.So it can improve the accuracy of the solution in the same calculation time.