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Analysis Of FinFET Fluctuation And Research On Relevant Circuit

Posted on:2019-10-01Degree:MasterType:Thesis
Country:ChinaCandidate:S ZhangFull Text:PDF
GTID:2428330590451644Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
The Moore's Law,as the "golden rule" of the integrated circuit industry,has led semiconductor devices to keep shrinking for several decades.Conventional planar MOSFETs have maintained excellent characteristics in deep submicron dimensions,but as the device scaling down to nanoscale,the short channel effect(SCE)become much severer,which greatly limits the development of planar MOSFETs.To cope with this problem and enhance the gate control capability of devices with small dimensions,a variety of multi-gate devices have emerged.FinFET is one of them.FinFET,Fin Field-Effect Transistor,named after its shape looking like a fish fin.Although it shows more excellent characteristics than the traditional MOS in SCE,with the size scaling down,the problem of intrinsic fluctuation due to the process variation has more and more effect on FinFET.However,the relevant research is lacking.The focus of this article is to simulate several kinds of process fluctuations in FinFET devices and analyze their effects.The first thing is to construct the device model,thanks to the previous research,there is a mature BSIM 3D model as a reference.At the same time,a 2D model is used for batch simulation,which can be well fitted with the 3D model and enhance the efficiency.Secondly,it is the use of simulation software.Sentaurus TCAD and GSS Tools can do well in generating models,simulating electronic feature and adding process fluctuation,which provide a reliable technical guarantee for the research.In the experimental part,this paper analyze the influence of fluctuation from the device level to the circuit level.The device level focuses on three kinds of fluctuations: Line Edge Roughness(LER),Metal Gate Granularity(MGG)and Random Discrete Dopants(RDD).The simulation parameters include the threshold voltage,the Drain Induced Barrier Lowering(DIBL)and IdVg.The circuit level starts from two directions: negative impact and positive utilization.The negative impact uses SRAM circuit as an example to analyze the harm of fluctuation to the stability and reliability of the SRAM circuit,and propose a method for suppressing the key fluctuation from the perspective of the circuit;the utilization part is to use the process fluctuation as the random source of SRAM-PUF,which provides reference and direction for the actual industry.
Keywords/Search Tags:FinFET, process fluctuation, SRAM, SRAM-PUF
PDF Full Text Request
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