CMOS-type Ising Chips And Applications

Nowadays,semiconductor technology has entered the era of 7nm,and farther improving semiconductor technology and architecture has become more difficult.In order to overcome the limitation of traditional microprocessor architectures,some non-von Neumann architectures have been proposed for special application fields.CMOS-type Ising chip is one of them,used to accelerate combinatorial optimization problems solving.To support large scale applications,the research of CMOS-type Ising chips focuses on reducing the hardware complexity,on the premise of enough precision.At present,the research faces many challenges in achieving high-precision local search,probabilistic state flipping and spins interconnection structures with low circuit overhead,and expanding application fields of Ising chips.To overcome the above problems,this paper proposes several optimization technologies.Firstly,we pre-add Ising model coefficients in problems mapping procedure to reduce the hardware cost of local search modules.And the number of local search modules is reduced by logic sharing technology.Secondly,the memory resources are fully utilized by memory reuse technology.Thirdly,the linear approximation probably computing technology is proposed to reduce the probably flipping overhead while guaranteeing the precision of ground state search.Fourthly,the pipeline type spin transition and update technology is used to reduce the all-to-all structure overhead.With the above technologies,we fabricate two Ising chips in the 28 nm CMOS process,and apply them in combinatorial optimization problems.Specially,we are the first to extend Ising chips into the domain of image segmentation applications.The main achievements of this paper are listed as follows:(1)We propose pre-calculating,logic sharing,and memory reuse technologies.The pre-calculating technology can reduce the total cost of Ising chips by 20%,or reduce the cost of non-memory part by 40%.The logic sharing technology can reduce the number of local search modules at the cost of larger time comsuption.In actual practice,we always take the 2-node or 4-node sharing structure,which has little effect on time comsuption.The memory reuse technology makes full use of Ising chips' memory resources.(2)We propose linear approximation probability computing technology and its circuit implementation.The linear approximation probability computing model can well meet the relationship between the probability of flipping over and the two model factors,energy barrier ?E and temperature T,and also avoid the transcendental function solver in probably flipping modules.Compared with exsiting simplified methods,the linear approximation probability computing model can improve the accuracy of the ground state search by 7.6%,confining the error within 1%(3)We propose a network-on-chip based all-to-all structure,and the pipeline type spin transition and update technology.Such technology can reduce the connection wire delay to 10%,which is better for achieving higher operation frequence.Moreover,such technology can effectively reduce the hardware overhead of spin state update circuits.Compared with the direct connection structure,our method can reduce the hardware overhead of spin state update circuits to 9%.(4)We fabricate two Ising chips in the 28 nm CMOS process.The one is local connection structure,for the domain of image processing.The other is full connection structure,for many more combinatorial optimization problems.Compared with exsiting ASIC-type Ising chips,our fabricated Ising chips have the widther coefficient-bit,the higher operation frequence,and the more accurate ground state search.(5)We are the first to extend Ising chips into the domain of image segmentation applications.We also apply our Ising chips into number partitioning problems.Compared with the traditional CPU-based methods,our Ising chips can efficiently improve the energy efficiency ratio.CMOS-type Ising chip is a promising way for ombinatorial optimization problems.This paper proposes several corresponding optimization technologies,including pre-calculating technology,logic sharing technology,memory reuse technology,linear approximation probably computing technology,network-on-chip based spin-interconnection technology,pipeline-type spin transition and update technology.These techniques help to reduce the hardware overhead of CMOS-type Ising chips while ensuring the precision.Moreover,we also propose the mapping method of image segmentation problems for Ising chips,which extends Ising chips into the domain of real-world applications.The evaluation results show that these technologies are practical and can be used in future CMOS-type Ising chips.