Improved Electrostatic Protection Design Of Power LDMOS

As the semiconductor chip manufacturing technology progress as well as the feature sizes decrease, the integrated circuit is becoming more and more compact and develops in a high density, so it is easy to suffer from the effect of electrostatic discharge(ESD). A minor ESD event, will even cause, permanent failure of the device. As a common power device, Lateral Diffusion Metal Oxide Semiconductor(LDMOS), has a good driving ability. In order to be compatible with the existing process, the high voltage ESD protective device which is modified by the LDMOS device can be used as an ESD protection on chip pins.In this paper, the electrical and thermal characteristics of LDMOS under ESD stress are analyzed in detail, and two new structures are proposed and verified by simulation software. The main research results include:1. The production process of ESD and test models are deeply analyzed. The physical models of ESD protection devices involved in the static pulse are also analyzed, which include physical transmission equation, band model, mobility ratio, avalanche model, Shockley-Hall-Read recombination and Auger recombination.2. In view of the conventional LDMOS devices’ low ESD resistance under ESD stress as a result of the high trigger voltage and surface current concentration, a new structure used to ease the concentration of surface current was presented and verified. By introducing the drift region with high and low doping concentration and the N-type buried layer, the new structure features low trigger voltage and high secondary breakdown current. The simulation results showed that the new structure had lowered the trigger voltage by 37% and enhanced the secondary breakdown current by 51%.3. Considering the high trigger voltage and the low hold voltage of conventional SCR-LDMOS devices, a new structure assisting the starting with PN junction was presented. The new structure introduces the PN junction to enhance the hole carrier concentration before the NPN BJT are started. This lowers the trigger voltage and enhances the hold voltage, with relatively better ESD robustness. According to the simulation results, the new structure lowered the trigger voltage by 44% and enhanced the hold voltage to more than twice.