FPGA Design And Implementation Of NAND Flash Controller And Optimization Of Finite Field Multiplier

In the past,due to the restriction of data storage and system speed,artificial intelligence and other technologies were once suppressed in the cradle.However,with the rapid development of non-volatile memory and large-scale storage devices,the amount of data that can be stored increasingly surges and the requirements of System data throughput speed become faster,which promotes the rapid development of artificial intelligence,big data and cloud storage.NAND Flash large capacity,which is easy to implement large-scale storage,has now become a mainstream non-volatile memory.Yet,Due to some problems of NAND Flash process itself and other issues,we need to combine the NAND Flash with the master to better work instead of directly using it as a memory.As a result,Solid-state drives(SSD)and eMMC are productions combining the NAND Flash and host controllers.With the solid-state hard drive,the system loads significantly become faster.Moreover,eMMC can be used in smaller storage devices,such as cell phones.All in all,Master is the core of SSD and eMMC since a good master chip or IP is the key to prevent NAND Flash from making mistakes.Based on the above considerations,this study aims to be committed to NAND Flash controller research and design work,including achieving a fully functional host controller,and the use of FPGA experimental verification,in order to lay the foundation of the subsequent realization of the main chip or IP core.The two main modules of the main controller are the error correction module and the block management module,which will be optimized and improved in this paper.First,the author changes the serial BCH error correction code to parallel codec and uses greedy algorithm to optimize the finite field multiplier;secondly,the block bad management algorithm applied in this paper is based on logical address mapping,and the author proposes a dynamic equalization loss model based on the ratio of valid pages and erasing times.In terms of the CAT algorithm,the CAT algorithm time interval factor is a kind of random variable.The different operations in different time periods of the system may exert different effects on the model.Nevertheless,the equalization loss algorithm in this paper can directly reflect the loss of the block.The main contents of this paper include:Firstly,the background of NAND Flash,the development of internal modules of its upgrade products(SSD,eMMC)and the situation at home and abroad are introduced.Then,the structure of NAND Flash and the sequence of reading.and writing are discussed in detail.The follow-up is to introduce the BCH error correction code designed for NAND Flash error flip shortcomings,involving changing it to 8bit parallel code to speed up the coding and decoding,and using greedy algorithm to optimize the finite field multiplication.Also,the finite field multiplier circuit is used in combination based on the consideration of the most suitable area and speed selection.Then,this paper introduces the system's block management module in detail,including bad block management,equalization loss and garbage collection,using the mapping table for block management instead of directly manipulating the physical block,which accelerates the system's speed.Besides,a model based on the effective Dynamic Equalization Loss Model for Page and Erase Times is proposed in this paper.In the last part,the realization of the system is presented.The system is made up of host computer,MCU,FPGA and peripheral circuits.It introduces the specific process of the module functions,such as read-write wipe and block management in the system,and the corresponding experimental environment is established to verify the correctness.