Design And Implementation Of BCH Error-correcting Algorithm Based On NAND Flash Controller

In some large national defense projects, in addition to the harsh testenvironment, test costs are very high, so as to save the cost of test, testequipment for the demanding reliability requirements, especially for the storageof data integrity and validity of the test has high requirements. NAND flash itshigh-speed, high storage density, seismic resistance, high temperature resistanceand other excellent features are widely used in national defense projectsdedicated data storage device. Since the structure and manufacturing processcharacteristics, NAND flash bit errors phenomenon exists. Error correction codetechnology for storage application can effectively solve the above data reliabilityissues. Dedicated data storage devices based on NAND flash controller, wedesigned and implemented a BCH error correction algorithm in firmware haspractical significance to improve the reliability of storage.Firstly, the BCH error correction algorithm is described in theoreticalresearch and System level simulation, specifically including environmentalestablishment (finite field overview and structure) algorithm, the characteristicsof linear block code and a description of cyclic codes, binary BCH errorcorrection algorithm parameters and significance select，followed by algorithmsoftware for functional verification, error correction algorithm described in detailthe functional verification step, as the foundation of firmware design,commissioning and optimization.On the basis of algorithm verification at the system level, BCH errorcorrection algorithm is designed using FPGA-based firmware, including the BCHencoder and decoder. The encoder firmware design describes the parameters ofthe analysis process and select,32-bit parallel encoder design and logicimplementation. Decoder firmware design first described analysis of the structureof a finite field firmware implementation process that generates the elements andalgorithms to build. Then according to the three-step decoding algorithm: thesyndrome calculation, error location polynomial determination and Chien search,we made a detailed analysis of error correction logic implementation. And Firmware algorithms for hardware verification platform, algorithms and datainteractively Flash controller and the host computer based on ZYNQ is described.In the last we had a systematic test for the firmware BCH error correctionalgorithm in the hardware validation platform, including simulation test, errorcorrection capability test, the rate change of the speed test for read and writ e, andresource utilization test. Test results validate the correctness of the algorithmdesign.