The Research And Realization Of Bad Block Management Algorithm For NAND Flash

After entering the new era of internet and the big data, high-capacity storage technology made a number of demands. The NAND Flash, especially a memory cell storing two bits data-MLC NAND Flash, has been greatly developed and applied, because of its advantages such as low power consumption, anti-vibration, highcapacity, small size, good random read and write performance, etc. However, due to the problems that block erase, page write operation logic results not matching wit h the current file system, the high stored data error rate and bad blocks, etc, make the existing disk management methods no longer applicable, and we must use NAND Flash management algorithm to make a management.Bad block management is one of the issues which must be addressed. Based on the study of used NAND Flash bad block management methods, we present a new bad block management solution. This solution uses bad block reserved area replacement policy in terms of strategy; in terms of bad block informati on storage, it uses a combination method of the bad block bitmap and a block address remapping table; in terms of the management process, static and dynamic bad block are separately managed. In the hardware adaptation layer, static bad block management module are designed to achieve the management of static bad blocks,and we designed the overall framework of the static bad block management, including bad block management initialization module, bad block management information table, bad block management controller module, hysteresis write module and other modules. Use FPGA logic timing in a manner to ensure the realization of complete bad block management function, and adapt with the upper FTL(Flash Translation Layer) transparently; in FTL layer,designed a nd implemented page granularity management strategy(PGMS) for dynamic bad block management. This strategy changed dynamic bad block management granularity the original coarse-grained block to the fine-grained page,which will take full account of the pages’ great reliability differences in resisting error growth within a block, in order to give full play to the potential life of all pages.In this paper, we implement this bad block management algorithm on self-developed NAND Flash hardware and software integrated verification platform based on Zynq. The PL(Programmable Logic) part in Zynq achieved static bad block management module which belongs to hardware adaptation layer, the PS(Processing System) part in Zynq achieved regular page mapping FTL algorit hm embedded dynamic bad block page granularity management strategy. Experimental results show that the management algorithm has advantages like high-speed(good block replacement need six clocks, bad block replacement need n * 6 + 4 + 2 clocks, average need 8 clocks), high reliability, low capacity overhead, high lifetime extension(in the 3x-nm manufacturing MCL NAND Flash can improve the lifetime about 35 times in the most).