Research On FPGA Code Function Verification Based On UVM

As a widely used device in the field of electronic design,FPGA has gradually increased its design complexity.Because FPGA often adopts Testbench based function verification mode,it can not meet the needs of stability and reliability of the increasingly complex design.In this thesis,the Universal Verification Methodology of integrated circuit verification-UVM is introduced into the domain of FPGA code function verification,and the design method and key technology of the FPGA code function verification platform based on UVM are studied.This thesis first studies the architecture and main operating mechanism of the verification platform based on UVM,and demonstrates the feasibility and technical advantages of using UVM to implement FPGA code function verification.UVM realizes the rapid establishment of a complete verification platform through reusability of module and parallel development characteristics.The modularized design of UVM enables the UVM verification platform has high reusability and development parallelism,transaction level data transmission guarantees high abstract level data transmission between UVM validation module,the verification based on coverage driven makes UVM verification complete and efficient,The phase mechanism ensures the automatic and orderly operation of the UVM verification platform.The function verification of FPGA code in UVM needs to accomplish the design of reference model and other modules.In the design of reference model,the register model is used to simplify the design of the reference model,the high efficiency of the test vector based on the constraint based random guarantee in the design of the test vector,Test vectors based on sequential mechanism have reusability and hierarchy,The function of driver and the design of data transmission interface,using register model to simplify the design of monitor and driver.Finally,taking the verification of CAN controller logic as an example,the method of building verification platform is studied.The verification platform built by Modelsim is used to simulate and analyze the results.It is proved that using UVM to build the verification platform of FPGA design is feasible and has high efficiency.It can greatly shorten the period of FPGA design,quickly locate the problem,and ensure the reliability and stability of the design.