Simulation Based System On Chip Verification Research

Verification has been one of the most important challenges to SoC design. Despite recent advances in formal verification, it can not meet the requirement of design. Simulation based verification method continues to be the workhorse. This dissertation addresses the issues of simulation based verification.Firstly, proposed and implemented coverage driven and GA(Genetic Algorithm) based Verilog RTL verification vector auto generation algorithm. Coverage information is fed back and form a closed system, the GA analyses dynamically the coverage information and selects the vector with higher fitness to generate the next generation vector. Secondly, proposed and implemented Domain fault model, coverage metrics and testing points selecting strategies. Domain fault model correctly reflects the reason causing domain errors, Domain coverage metrics measure the quality of the verification approach, and test point selecting strategies generate required points for domain testing. Thirdly, implemented a C reference model and SVA(System Verilog Assertion) based function checking method. Lastly, proposed and implemented a C based SoC chip level verification method, in which a cycle accurate AMBA functional model is connected to ARM ISS and the devices on bus are translated from Verilog RTL.Preceding methods are used in Garfield series SoC2 verification approach. When doing block level verification, GA based Verilog RTL verification vector auto generation algorithm is used to generate the verification vector, results show that the algorithm can generate vector more quickly and reach higher coverage than directed and random method. Domain method is adopted to measure block level verification quality, domain coverage metrics can find more verification holes, compared with line and path coverage metrics. C reference model and SVA based checking method are also used in the block verification approach, results show that this method can reduce greatly verification time and human resource, locate the design error quickly. When block level verification reaches the required domain and functional coverage, the C based SoC chip level verification method is used to verification whole chip, results show that whole chip can be verified at speed of 20 times of Verilog RTL simulation.