The Research And Implementation Of Gigabit Ethernet Test System Based On FPGA

With the rapid expansion of computer networks, Ethernet has been widely used because it has the properties of widespread and convenient access. Gigabit Ethernet technology is built on the basis of the Ethernet standard, and it has become the mainstream of network technology because of the characteristics of high efficiency, high speed and high performance. With the rapid development of High-speed network and its products, it puts forward higher requirements for network equipment. Tts performance has a direct impact on network size, stability, and reliability. Therefore, the network test equipment requirements are also increasing. It becomes more and more important and urgent to develop a reliable and stable test system. At present, the network testing instruments market in our country is basically monopolized by foreign manufacturers, and international well-known network testing instruments is very expensive. The implementation technology is more complex, and the operation is not flexible enough. This paper aims to develop a network testing tool, which is practical, operated flexible, low price and has good performance. The main work and achievements are as follows:1. On the basis of the existing network test system, a set of gigabit network test system scheme based on FPGA is put forward. The working principle of the system is introduced. A set of network testing system frame format is customized on the basis of in-depth analysis of the Ethernet protocol and TCP/IP system. The frame format contains Ethernet testing frame format, control instructions frame format and data instructions frame format to meet the needs of network test system.2. FPGA is selected as main controller, according to the system hardware circuit design goal and modular design thought, the hardware schematic and PCB multilayer circuit board are designed by using the Altium Designer software, after installation, welding and debugging, the network test system hardware platform is implemented, and the process of debugging hardware circuit is analyzed and summarized.3. The principle of CHECKSUM algorithm and CRC32algorithm is studied, and the VerilogHDL language hardware implementation of the algorithm is completed. The system software design and implementation of each function module are completed on the hardware system platform of this project. At the same time, the PC control terminal application software is developed.In this paper, the whole system and its every function module are tested. Finally, the paper is summarized, and some prospects are put forward for further research.