Research On Topology Generation And Mapping Opimization Algorithm Of Application On-chip-network

With the continuous development of semiconductor technology,the communication architecture based on the traditional bus architecture as a system on chip(SoC)has been unable to meet the communication needs among various IP cores.In order to solve the shortcomings of bus structure as a communication architecture,the proposal of Network on Chip(NoC)becomes an effective solution.When using the Network on Chip for chip architecture design,the specific design of the Network on Chip needs to be performed due to the performance constraints of chip area,power consumption and the like.However,many fundamental theoretical and technical issues still remain in the area of Application-Specific Network-on-Chips(ASNOC)design.This is mainly due to the issue of how to generate an overall balanced Topology and a more efficient mapping scheme to find a better objective function.Therefore,this thesis focuses on these two aspects and proposes a multi-target topology generation method and a mapping optimization method for the Application-Specific Network-on-Chips.The main work is as follows:(1)Multi-target Application-Specific Network-on-Chips topology generation method research based on delay and fault tolerance.For the disadvantage of the overall performance of the topology generated by the single-target topology generation method,The first a multi-objective topology generation model based on delay and fault tolerance is established based on the linear weighted method,and then the single-pass topology generation method is used to generate the single-pass topology Based on this,a set of multi-path topology sets are generated by adding the links and routes.Finally,through the above-mentioned multi-objective model,the optimal topology of the objective function is selected from the multi-channel topology set.Compared with the topologies generated by other single-target topology generation methods,the topological structure generated by the topology generation method in this paper has lower delay and better fault tolerance,and the overall performance of the topology is better.(2)Optimization of Application-Specific Network-on-Chips mapping algorithm based on power consumption.First,This thesis analyze the mapping power consumption of the Application-Specific Network-on-Chips and establish the mapping power model.Secondly,according to the characteristics of the Application-Specific Network-on-Chips topology,the task nodes are clustered based on the traffic to reduce the mapping power consumption value and reduce the search space.Finally,the simulated annealing algorithm with memory module is used to find the optimal mapping scheme for power consumption.In order to combine with the practical application,this thesis compares the power consumption of the current commonly used multimedia task graph with simulated annealing algorithm,genetic algorithm and stochastic mapping algorithm to prove the superiority of simulated annealing algorithm in the Application-Specific Network-on-Chips mapping.At the same time,the thesis also compares the power consumption between the clustering and the non-clustering task graph.The experimental results show that when the number of task nodes increases,the use of clustering and then mapping has some advantages in power consumption and convergence speed.