Performance Optimization Of Network-on-Chips With Accelerating Network

In multi-core system, every core needs to send and receive data and control information from each other. Communication between cores has already been the bottleneck of the development of multi-core system. Network-on-Chips (NoCs), which solve this problem by distributing communication, is a popular research area for multi-core system. However, long distance communication problem has risen since the growing of cores on Network-on-Chips. High performance solution for long distance communication is to borrow accelerating network. At present, the study of accelerating network mostly focuses on hardware realization, less effects has been done to analysis how to optimize the performance of Network-on-Chips with Accelerating Network (ANNoC) from computer architecture level.This paper first analysis the architecture of ANNoC, and model its performance from topology, routing and mapping. Then, the paper studys the number and layout of accelerating nodes, routing strategy and mapping strategy for ANNoC in detail, and proposes methods to optimize the performance of ANNoC. There are three main topics in this paper:(1) Methods to optimize topology in ANNoC. This paper compares three communication optimization goals, which are minimizing the maximum distance, minimizing the average communication distance and minimizing the sum of distances between each node and accelerating network. Experiments show minimizing the average communication distance is the best choice. With this communication optimization goal, this paper proposes a method for how to choose the number and layout of nodes in accelerating network, as well as a method for layout of accelerating nodes under large scale NoC.(2) Methods to optimize routing algorithm in ANNoC. This paper discusses four routing strategies, which are2D-mesh only routing, always accelerating network routing, accelerating network first routing and2D-mesh network first routing. Among them,2D-mesh network first routing shows better performances under different circumstances. This work also proposes a link reservation strategy to reduce the heavy link load near accelerating nodes.(3) Methods to optimize task mapping in ANNoC. The paper analysis the difference between mappings under ANNoC and a2D-mesh NoC. Then, the paper gives two mapping algorithm, MGA for optimizing global mapping, and ANCR for optimizing local mapping.Experiments show that, for a Network-on-Chip with64cores, four accelerating nodes distributed under the goal of minimizing the average communication distance using2D-mesh network first routing algorithm is the best choice. The link reservation strategy reduce12.5%link load near accelerating nodes under uniform traffic distribution model. MGA and ANCR reduce28.8%and15.6%total communication cost respectively, as well as17.4%and10.2%reduction on network latency.In a word, the optimizing methods introduced in this paper can improve efficiency of accelerating network, reduce link load of the network, enlarge the throughput of the network and reduce communication cost and network latency for tasks.