Design And FPGA Implementation Of Memory Reduced Turbo Code Decoder For LTE-advanced Standard

Channel coding is one of the key technologies to guarantee reliable information transmission in wireless communication systems.Due to the error correction performance near to the Shannon limit,Turbo codes have attracted great attention and been employed as channel coding scheme by various communication standards.Nowadays,Turbo codes have been adopted for the LTE-Advanced standard.In the engineering realization of Turbo code decoder,the decoding algorithm is iteratively performed to obtain the satisfactory bit error rate(BER)performance.Because of the properties of the decoding algorithm,the decoder requires large capacity memory and frequent memory accessing.As a result,the power consumption of Turbo decoder is high.Therefore,for the energy-constrained wireless communication applications,the power issue of Turbo decoder is considered as one of the most important bottlenecks.In order to address this deficiency of Turbo decoder,a memory reduced decoding architecture has become a hot topic of the research.In Turbo decoder,there are mainly three kinds of storage units: the soft received bits memory,the soft extrinsic information memory and sate metric cache(SMC).Among them,SMC has the largest capacity and frequent access operations,which has the great influence on the overall power consumption of the decoder.Thus,it is an effective strategy to reduce the total power dissipation of Turbo decoder by decreasing the SMC capacity.This thesis firstly introduces the basic principle of the Turbo encoder and decoder,and detailedly deduces and analyzes the maximum a posteriori(MAP)decoding algorithm and its variants.Then,the decoding scheme based on the smooth compressing state metrics is proposed.By inserting a compression module and a decompression module in the conventional Turbo decoding architecture,the compressed state metrics can be stored in the SMC with smaller quantization scheme,and then are estimated by using the correlation.The results show that this solution reduces the SMC capacity by 38.75%.Inspired by this design idea,in order to further cut down the SMC size,a method based on cyclic compressing state metrics is researched.This technique reduces the SMC capacity by 53.75% by recording the times of the iterative compressions.Although the two design methods based on the compression calculation can achieve the purpose of reducing the power consumption of Turbo code decoder,they inherently belong to lossy compression strategy,and the BER performance has a certain loss.For this reason,a decoding architecture based on reverse recalculation is also investigated.By using the reverse recalculation,only half of forward state metrics need to be stored in the SMC.The results demonstrate that this scheme reduces the SMC capacity by 50% and the decoding performance is very close to that of the maximum a posteriori probability in logarithmic domain(Log-MAP)algorithm.Finally,by using the Verilog hardware description language(HDL),this thesis realize all the decoding modules based on the reverse recalculation in the Quartus?13.0 software.