Research And Implementation On FPGA Platform Of Low Complexity Turbo Product Code Decoding Algorithm

With the rapid development of wireless communication technology,increasing attention has been paid to the reliability of information transmission.Turbo product codes,as a kind of linear block codes with high coding efficiency and good error correction performance,has great research value and application potential.In recent years,it has become a hotspot in the field of channel coding.However,the traditional Chase iterative decoding algorithm of turbo product codes is quite complex,which makes it not suitable for hardware implementation.Therefore,how to improve the Chase iterative decoding algorithm in order to obtain a reasonable tradeoff between decoding performance and complexity has become the research focus of turbo product codes.This thesis focuses on the encoding and decoding technology of turbo product codes.In this thesis,a low complexity decoding algorithm is studied and selected,and after which the hardware design and implementation are presented on FPGA platform.The main contents of this thesis are as follows:1.The encoding and decoding principle of turbo product codes are described systematically,and the Chase iterative decoding algorithm and its improved low complexity algorithm are studied profoundly.Besides,the performance difference between the original algorithm and the improved algorithm is analyzed by simulation,which shows that the improved low complexity decoding algorithm of turbo product codes in this thesis can obtain 6.8dB coding gain under bit error rate of-610.2.The hardware design and implementation of the low complexity Chase iterative decoding algorithm are presented on FPGA platform,and the pre-layout simulation of the decoder circuit is carried on,which shows that the coding gain of code blocks is less than 0.1dB in the main range of bit error rate,compared with that in the floating point simulation.3.The futher validation and performance analysis of the decoder circuit are finished on Altera DE5-Net FPGA development platform,which shows that the decoder of turbo product codes has a low resource utilization,while its maximum working frequency can reach to 333 MHz.Besides,the real time decoding rate of the decoder reaches to 33 Mbps and the decoding delay reduces to 248 ?s.The research and implementation has indicated that the low complexity decoding algorithm of turbo product codes selected in this thesis and the decoder designed based on it can meet the requirements of the project.