Key Technology Research And Implementation Of Linear-array Image Scanning System Based On C64x DSP

In the fields of banking and securities,the digital processing of documents and bills is a development trend.Common scanners,high-paced cameras,etc.are commonly used devices for digitizing images,but these devices take up space and have additional costs.Integrating image scanning functions into printers,card readers,and other devices is a trend.In this type of equipment,it is necessary to develop a dedicated linear-array image scanning subsystem,which includes two key technologies: image real-time coding technology and FPGA online configuration technology.This article focuses on two key technologies in the new linear-array image scanning system.First of all,in order to meet the needs of the system to scan images at high speed,this paper has studied the principle of the JPEG encoder and implemented the JPEG real-time encoding compression on the C64 x DSP.In order to optimize the quality of the input image to improve the coding efficiency,an image correction algorithm based on point-by-point compensation is designed in this paper,which eliminates the noise of the scanning image.In order to meet the requirements of image scanning speed,this paper optimizes the encoder implementation codes based on instruction level optimization,algorithm optimization,and memory management optimization,and significantly improves the JPEG encoding speed.Then,for the need of FPGA maintenance and upgrade in the scanning subsystem,this article design a FPGA online configuration method based on the host processor and optimizes the configuration speed.In the application,the FPGA configuration file is saved as data in the firmware of the DSP.After the system is powered on,the DSP writes the configuration file to the FPGA chip through the JTAG interface,eliminating the configuration chip in the traditional FPGA configuration method and reducing the design costs,also facilitate the remote upgrade of the FPGA.Finally,the above results are integrated into the image scanning subsystem and tested in actual devices.The JPEG encoder has reliable performance.The scanning speed is improved by approximately 4.5 times before the encoder is optimized.The FPGA online configuration function of the host processor is normally stable,and the FPGA chip configuration time is less than 1.2 seconds,which is about 1.7 times faster thtough the optimization.The products developed based on the results of this article have been produced on a large scale and the functions and performance have been tested.