FPGA-based Image Acquisition And Transmission

With the continuous development of electronic technology and computer science,the development of computer vision has become a very important development direction.Whether it is the traditional surveillance industry or the emerging Internet of things,automatic driving,high-speed bayonet detection and other emerging industries,computer vision is an essential component,and the basis of this component is the image acquisition and transmission.With the development of computer vision and image processing technology,the requirements for image quality are also getting higher and higher,and there are more requirements for the flexibility of the image display mode.The traditional DSP or microcontroller-based image acquisition has been difficult to meet the requirements,and the flexibility of the VGA or HDMI display is also limited.In this context,this paper designs a FPGA-based image acquisition and transmission system,which can not only use the traditional VGA,HDMI,etc.,but also can be transmitted to the network via Ethernet.Using FPGAs as the basis for acquisition and transmission overcomes the drawbacks of the lack of flexibility and expense of using dedicated hardware and the use of FPGA parallelism to implement high-definition image acquisition systems that can be quickly processed if needed.Transmission via Gigabit Ethernet allows for flexible presentation at remote terminals,such as through multi-terminal applications or via web pages.In this paper,the image acquisition,display and transmission functions are implemented on the Xilinx Spartan 6 processor and a simple PC host program is developed to show the image data received from the network.The system implemented in this paper can not only be used in the traditional video surveillance industry,but also used in machine learning and artificial intelligence.Because of the characteristics of FPGA parallelism,making it an excellent platform for the operation of machine learning algorithms,the system implemented in this paper is equivalent to the input and output of these algorithms is an indispensable condition.