Research On Die To Die Interconnects Test Methods For Three Dimensional Integrated Circuit

Three dimensional integrated circuits(3D IC)connect the vertical stacked multi-layer die with through silicon via(TSV)technology,which not only improves the chip's integration density,but also has the advantages of high bandwidth,low power consumption and heterogeneous integration.As the mainstream technology of the next generation of chip design,3D IC will gained tremendous momentum for the development of the semiconductor industry.At the same time,3D IC is also facing new challenges in its manufacturing technology,testing,heat management,interconnection design and CAD algorithms and tools.In the manufacturing process of the chip,immature manufacturing processes are very easy to bring many physical defects to die-to-die interconnects,and the later they are found,the greater the loss will be.During the use of the chip,electromigration and thermal stress also lead to some physical defects to die-to-die interconnects,which will also cause the chip failure.Therefore,the production yield and of 3D integrated circuits and the reliability of normal work are closely related to the quality of the die-to-die interconnects.There are still many shortcomings in the existing methods of pre binding test and On-line test for the die-to-die interconnects.In order to ensure the commercial viable of the 3D IC,the die-to-die interconnects testing technology must be further improved.To tackle the above problems,this paper propose the complete pre-bond test and On-line test scheme for the die-to-die interconnects to improve the chip yield and reliability.In the pre-bond test,two methods of CAF-WAS and pulse shrinking are proposed;in the aspect of On-line test,a method of distributed cursor is proposed.The main contribution in the dissertation is as follows:1.CAF-WAS based pre-bond through silicon via test.Though Silicon Via(TSV)open/short defect reduces the reliability and yield of three-dimensional integrated circuit,so TSV testing before bonding is especially important.Put forward a new CAF-WAS(Charge and Float,Wait and Sample)based on pre-bond TSV defect test methods.Pseudo leak path thought is put forward to solve the existing CAF-WAS methods cannot be carried out on the open defect test.In addition,the circuit to redesign the waiting time,reduce the testing time overhead.HSPICE simulation results show that this method can accurately forecast the open defect and the scope of the leakage defect,test time spending only 25% of the existing methods.2.Pulse shrinking based pre-bond through silicon via test.There are some shortcomings in the existing pre-bond TSV test techniques,such as incomprehensive fault coverage,large area overhead,and long test time.To cope with these problems,a solution for pre-bond TSV test based on pulse shrinking is proposed to diagnose the faults of TSV.Defects in TSV lead to variation in the propagation delay,the rise and fall time is transformed into pulse width individually,and then the pulse shrinking technique is used to digitize pulse width into a digital code to compare with an expected value of fault free.This method not only has a larger detection range in the single fault test,but also can diagnose the multiple fault phenomena that exist at the same time in the open and short faults.Experimental results show that pulse shrinking method is superior to existing methods in fault coverage,measurement range,area overhead and test time,and also has good reliability.3.Distributed vernier based die-to-die interconnects testing.In order to solve the several problems in the existing interconnect test methods,such as poor applicability,high area overhead and resolution instability.Puts forward a technique for interconnect testing based on distributed vernier method.First of all,two kinds of vernier structures,including regular vernier and ring veriner designs,were selected according to the number and distribution of interconnect.Then,all the delay cells of the vernier delay line are evenly distributed to each interconnect,so that all interconnects share the same vernier delay line.Finally,the interconnect delay was quantized into digital code.The experimental results show that,the test time and area overhead are both considered,which can meet the requirements of complex integrated circuits design.The area overhead of the two distributed veriner methods are decreased by 52.6% and 23.7% respectively,compared with the existing methods.When the distance between adjacent interconnects changes,the stability of the measurement resolution is improved by 70%.