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Research On Pre-bond TSV Test Methods For Three Dimensional Integrated Circuit

Posted on:2017-04-04Degree:MasterType:Thesis
Country:ChinaCandidate:Y LiuFull Text:PDF
GTID:2308330488495462Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
TSV Based Three-dimensional integrated circuits(3D ICs) has greatly promoted the development of the integrated circuit industry. Different from two dimensional integrated circuits,3D ICs stack dies vertically by TSVs with many advantages, such as low power consumption, high bandwidth, small size, good performance, heterogeneous integration supported and so on. However, the current manufacturing process of TSV and bonding technology is still infant, variety of defects may happened in TSV, reduced the yield and the reliability of 3D ICs severely. So it is necessary to test the TSVs in 3D ICs. There are pre-bond TSV test and post-bond TSV test in TSV test. Pre-bond test is mainly to detect whether there are manufacturing defects in TSV as well as post-bond test is mainly to detect the new defects in the bonding process. The stage of pre-bond without wafer thinning, the bottom end of TSV embedded in the substrate and limits the accessibility. After the wafer thinning, the probe test of TSV is also difficult in probing TSV although exposed to the bottom of the TSV. The pre-bond TSV test faces the huge challenge. In view of the problems above, some research works related the pre-bond TSV test are as followings:1.The basic knowledge of 3D ICs and the manufacturing process of TSVs are investigated, and the TSV defects may exist in the manufacturing process of 3D ICs are researched. The TSV fault caused by TSV defects is analyzed, the electrical parameters model of fault TSV is established, and the fault effect of fault TSV is investigated.2.The exist TSV test methods is researched. There are pre-bond TSV test and post-bond TSV test according to the test phase, the TSV test method based on probe and BIST according to the test principle. We focused on the BIST test method in the pre-bond TSV test. The pros and cons of existing pre-bond TSV test methods based on BIST is analyzed. We explored the new pre-bond TSV test method based on the existing theory.3.A pre-bond TSV test method using arbiter is proposed. The high level signal delay of faulty TSV is shorter than fault-free TSV’s. So the delay of TSV under test is compared with fault-free TSV’s, the faulty TSV is detected and the test results are outputted by the arbiter. Furthermore, comparing the delay of TSV under test with different equivalent delays, the delay of TSV is mapping into preset intervals and TSV fault is graded. Experimental results show that the proposed method is able to detect the TSV with resistive open fault and leakage fault, and solve the problem of the detection of TSV with two faults effectively. The proposed method expands the scope of fault detection, achieves higher precision and fault gradation compared to previous works.
Keywords/Search Tags:Three-dimensional integrated circuits, through silicon via, pre-bond test, resistive open fault, leakage fault
PDF Full Text Request
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